AMD Bulldozer Core Patent Diagrams

Hmm, I thought there was something to do with multiple power planes that AM2+ didn't support?
Or was that AM2 -> AM2+ :???:

that mobo has a great slots layout
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Yeah it is nice. I've got a V1.0 with my Thuban in it.
I had been going to get an FX model for the IOMMU but heck if I'm gonna pay an extra NZ$100 (about 1/3 premium) for that while losing the onboard GPU.
 
Well my AM2+ boards don't have the ACC overclock feature but that's it. I have a GF 8200 board and some 780G+SB700 boards around. You need SB750 or later for ACC and that was a later AM2+ chipset so it's probably not very popular.

You can even put AM3 chips in some original AM2 boards. The Gigabyte MA74GM-S2H (740G + SB700) (CPU list) can run almost all AMD CPUs as long as you don't go beyond what the VRMs can handle. However in this case the HT bus drops to the classic 2000 MT/s rate. In practice I think this is mostly detrimental to IGPs because they have so little bandwidth for their memory access.
 
this is what I run, an AM3 Athlon X2 in a vanilla AM2 motherboard. some more power is used because of the lack of a separate voltage rail for the memory controller, this is way AM3 and AM2+ 125W CPUs are incompatible, but all others do work. nobody cared to support 95W phenom II X6, maybe because they are rare CPUs (the lowest retail X6 usually is the 125W 1055T)
 
Data speculation is generally pie in the sky ... speculative execution is pretty much standard on most processors though (can't really do branch prediction without it, since you can obviously predict wrong).
 
hoom said:
Dresdenboy found the official programming guide for Bulldozer.

Amongst the bits officially stated there is Speculative Execution.
I thought that had been written off as pie-in-the-sky stuff?
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As soon you (mis)predict branches you have "Speculative Execution".
I think you meant "reverse hyper threading" (I doubt theres an official term there is for this since no one would seriously consider it), where multiple paths are executed concurrently on several cores/threads?
 
It's strange to see the L1 data cache latency increased by 33% and at the same time its size being just a quarter, compared to the previous AMD architectures.
The L2 cache is also not the fastest implementation around, but the good news is that it's partially inclusive in relation to the L1 data caches, which avoids costly write cycles.
 
fellix said:
It's strange to see the L1 data cache latency increased by 33% and at the same time its size being just a quarter, compared to the previous AMD architectures.
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Increased by 33% when measured in cycles, not when measured by absolute time.

I see two reasons for this

1) Nice clock speed improvements coming
2) The advancements in memory reordering may have slight impact on L1D latency.

The L2 cache is also not the fastest implementation around, but the good news is that it's partially inclusive in relation to the L1 data caches, which avoids costly write cycles.
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The problem here is that there is both small L1D and slow L2 cache. Means L1D misses will be more common than with K7/K8/K10 (about as common as with sandy bridge) but they will take more cycles than with sandy bridge.
 
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well is it a 6-core CPU, or six CPU, or three dual core CPU ;)
and what about a core2quad or a socket G34 opteron (they work in the same way as two separate CPU from the same vendors)
the whole CPU/core distinction is pretty arbitrary.
 
I'm not sure how worthwhile those numbers are.
At least in part, it's an engineering sample, and in part because I don't have a decoder ring wide enough to fit that chip descriptor.
It may only be 6 cores, and I don't have an idea on what the methodology was.
 
fellix said:
:nope:
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Uhm. Judging the platform by some pictures on the internet is extremely premature at best. Just looking at those 3DMark06 numbers, they are in Athlon II + HD4870 territory (with a 6970). Even if final silicon Zambezi were to end up uncompetitively slow, those results doesn't make much sense unless that setup is hamstrung by other factors than an early engineering sample CPU.
 
3dilettante said:
I'm not sure how worthwhile those numbers are.
At least in part, it's an engineering sample, and in part because I don't have a decoder ring wide enough to fit that chip descriptor.
It may only be 6 cores, and I don't have an idea on what the methodology was.
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Judging by this thread http://www.chiphell.com/thread-189079-1-2.html it seems it is indeed both a six core (not eight) and earlier revision (A1 as opposed to B0 apparently) than the current ones.
 
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