XDR2? ...
Memory configuration is going to be a major feature next gen. With many-cores, high-bandwidth GPUs, and slow optical media *something* will need to give. If past CPUs are an indication CPU cache will be limited, further increasing the needs for fast memory to feed the CPUs.
I know devs loved the split configuration on the PS3, but maybe we will see a small pool of very, very fast memory and a large pool of slower. Maybe in this context a very large scratchpad makes sense (but also expensive).
I guess that is the benefit of waiting until 2012. But then again if, say, the GPU continues on the path of Xenos (i.e. memory controller is there) and eDRAM is dropped (and that package+wiring) and that budget is incorporated into the GPU, maybe the GPU will be of significant enough size to justify a 256bit bus. There are affordable retail GPUs out there with 256bit busses and if the GPU is significantly large (Xenos+eDRAM is about 330mm2) they may budget it so a full process shrink can still fit a 256bit bus?
If they plan to use DirectCompute/OpenCL for utilizing the GPU for post processing (stuff SPEs are doing on the PS3), physics, and other math tasks this may be a feasible approach?
Memory configuration is going to be a major feature next gen. With many-cores, high-bandwidth GPUs, and slow optical media *something* will need to give. If past CPUs are an indication CPU cache will be limited, further increasing the needs for fast memory to feed the CPUs.
I know devs loved the split configuration on the PS3, but maybe we will see a small pool of very, very fast memory and a large pool of slower. Maybe in this context a very large scratchpad makes sense (but also expensive).
I guess that is the benefit of waiting until 2012. But then again if, say, the GPU continues on the path of Xenos (i.e. memory controller is there) and eDRAM is dropped (and that package+wiring) and that budget is incorporated into the GPU, maybe the GPU will be of significant enough size to justify a 256bit bus. There are affordable retail GPUs out there with 256bit busses and if the GPU is significantly large (Xenos+eDRAM is about 330mm2) they may budget it so a full process shrink can still fit a 256bit bus?
If they plan to use DirectCompute/OpenCL for utilizing the GPU for post processing (stuff SPEs are doing on the PS3), physics, and other math tasks this may be a feasible approach?