360 CPU Design

SubD

Newcomer
Does anyone know why IBM went with three cores all sharing a single cache in the 360 CPU?

From all the PPC coding I've over the years, I would think it would have been easier to go with a standard dual core PPC chip. The reports from developers on the performance differences between the devkits seems to indicate that real world performance is on par with a 2 to 2.5 GHz dual core 970 chip.

Having to share a single cache for three cores sounds like a lot of tedious and careful data placement and management for 360 developers.
 
SubD said:
Does anyone know why IBM went with three cores all sharing a single cache in the 360 CPU?

From all the PPC coding I've over the years, I would think it would have been easier to go with a standard dual core PPC chip. The reports from developers on the performance differences between the devkits seems to indicate that real world performance is on par with a 2 to 2.5 GHz dual core 970 chip.

Having to share a single cache for three cores sounds like a lot of tedious and careful data placement and management for 360 developers.

Sharing the cache also has advantages, it allows fast communication between the cores and it completly removes the stale data problem. Two cores can work simultaneously on the same data block without penalty as long as they are not working on the same cache line.

But it's likely as much for cost reasons as it is for technical reasons.

My bet is that the Xenos core produces considerably less heat than a dual core 970.
 
Lifted from The Inquirer, but regardless it gives you a date to shoot for SubD:

MARKET RESEARCH firm In-Stat said that IBM will deliver what it calls three "blockbuster" presentations at its Fall Processor Forum.

In-Stat said the presentations will include technical details about software development for the Playstation 3, the microarchitecture of the triple core Power PC in the Xbox 360, and details of a brand new dual core Power PC G5-class CPU.
 
SubD said:
Does anyone know why IBM went with three cores all sharing a single cache in the 360 CPU?

From all the PPC coding I've over the years, I would think it would have been easier to go with a standard dual core PPC chip. The reports from developers on the performance differences between the devkits seems to indicate that real world performance is on par with a 2 to 2.5 GHz dual core 970 chip.

Having to share a single cache for three cores sounds like a lot of tedious and careful data placement and management for 360 developers.

The peak vector execution rate is (or should be) nearly twice that of a dual 2.5GHz G5, it'll also run considerably cooler.

Cache per core would create a larger die and raise costs. Shared cache also has advantages as pointed out above, POWER4/5 and Intel's next gen also use them.

One thing Xenon can do is "stream processing" where data is processed in stages across different cores. This avoids going to RAM, without a shared cache this won't work.
 
ADEX said:
One thing Xenon can do is "stream processing" where data is processed in stages across different cores. This avoids going to RAM, without a shared cache this won't work.
What of the opteron, with its hypertransport link between cores?
 
ADEX said:
One thing Xenon can do is "stream processing" where data is processed in stages across different cores. This avoids going to RAM, without a shared cache this won't work.

Local Storage anyone ;) ?
 
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