22 nm Larrabee

Discussion in 'Architecture and Products' started by Nick, May 6, 2011.

Tags:
  1. dnavas

    Regular

    Joined:
    Apr 12, 2004
    Messages:
    375
    Likes Received:
    7
    Hmm, I missed that -- where did you see that?
    I see 256GB NVRAM (whatever that means) with 1.6TB/s and 16TF, and I see 1024 L2s, but not seeing onboard sram sizes -- you must be looking at a different slide?
     
  2. Man from Atlantis

    Regular

    Joined:
    Jul 31, 2010
    Messages:
    732
    Likes Received:
    6
    and GK110 has tons of non compute stuff.. imagine how many more cores could nv have added instead.. not to mention a full node handicap
     
  3. rpg.314

    Veteran

    Joined:
    Jul 21, 2008
    Messages:
    4,298
    Likes Received:
    0
    Location:
    /
    That slide has been going around for a while. It says each L2 is 256K.
     
  4. gl33k

    Newcomer

    Joined:
    May 31, 2007
    Messages:
    65
    Likes Received:
    1
    SRAM is the memory used for L1/L2 cache right ?
    jesus , 256MByte of this would be devastating
     
  5. Blazkowicz

    Legend Veteran

    Joined:
    Dec 24, 2004
    Messages:
    5,607
    Likes Received:
    256
    NVRAM can also be MRAM or whatever available (plain DRAM with battery or supercapacitor backup also qualifies, it's why you lose your BIOS settings if you remove the coin shaped battery on your motherboard. You've got NVRAM there)

    But, I assumed these 256GB are not the NVRAM. Did you miss the multiple "DRAM cubes"? :). 256GB are on multiple stacks of DRAM on interposer, that's not too bad either.
     
  6. dnavas

    Regular

    Joined:
    Apr 12, 2004
    Messages:
    375
    Likes Received:
    7
    Oh, non-volatile. Hah, I'll not embarrass myself and explain what I thought it stood for :>

    Well, I'm running on memory here, but it seemed like that was on-chip, and I had trouble imagining 256GB on an interposer. Some serious potential bandwidth with 256GB onboard....
     
  7. Blazkowicz

    Legend Veteran

    Joined:
    Dec 24, 2004
    Messages:
    5,607
    Likes Received:
    256
    I now have trouble imagining 256GB on interposer too but it doesn't feel too impossible in 2020 for the highest end chip ever. They would kind of max out the tech.

    I believe there was confusion with rpg.314 reading 256 MB and concluding it was SRAM, but I'm 100% sure 256 GB is written there.

    for 256GB that could be eight times a pile of eight stacked memory dies, with 4GB i.e. 32Gbit per unit of memory (not too far of contemporary 4Gbit chips). Of course this doesn't really exist, nor a 10nm process. I hope 2020 is a far away enough date, these techs are maybe the far end of current realistic R&D.

    PS : well it can be 128GB "D-RAM cubes" and 128GB NVRAM or something.
     
    #1107 Blazkowicz, Nov 26, 2012
    Last edited by a moderator: Nov 26, 2012
  8. iMacmatician

    Regular

    Joined:
    Jul 24, 2010
    Messages:
    773
    Likes Received:
    200
    Does anyone know anything about this (from many months ago)? Is this reliable in any way?

    I would expect something like half of those numbers.
     
  9. rpg.314

    Veteran

    Joined:
    Jul 21, 2008
    Messages:
    4,298
    Likes Received:
    0
    Location:
    /
    Then may be on 10nm we'll see Intel bringing LRB cores on die.
     
  10. Blakhart

    Newcomer

    Joined:
    Sep 27, 2006
    Messages:
    103
    Likes Received:
    0
    Is lrb going to be produced and released?
     
  11. rpg.314

    Veteran

    Joined:
    Jul 21, 2008
    Messages:
    4,298
    Likes Received:
    0
    Location:
    /
    Yes, in the form of HPC accelerators called Xeon Phi.
     
  12. Frontino

    Newcomer

    Joined:
    Feb 21, 2008
    Messages:
    84
    Likes Received:
    0
    I have a doubt about Knights Corner specifications: I know that each core has a 512 bit vector processor, but is it a single unit capable of multiple operations at lower width (32 & 64 bit) in the same cycle or is it composed, like some table shows, by a 16-way 32 bit and an 8-way 64 bit vector unit? Wouldn't that make the processor actually 1024 bit wide?
     
  13. Gipsel

    Veteran

    Joined:
    Jan 4, 2010
    Messages:
    1,620
    Likes Received:
    264
    Location:
    Hamburg, Germany
    It's the former. It either processes 16 32bit float operations or 8 double operations. It basically works the same as the SSE or AVX units, it's just wider.
     
  14. Frontino

    Newcomer

    Joined:
    Feb 21, 2008
    Messages:
    84
    Likes Received:
    0
    Thanks, Gipsel.
     
    #1114 Frontino, Mar 11, 2013
    Last edited by a moderator: Mar 14, 2013
  15. LiXiangyang

    Newcomer

    Joined:
    Mar 4, 2013
    Messages:
    81
    Likes Received:
    47
    MiC's L1 cache is not programmable, the inter-thread commuications on MiC is pretty much like the case of CPU. Intel's developer's forum is near, I will definitely go there to verifty if my experience with MiC is merely an exception.
     
    #1115 LiXiangyang, Apr 8, 2013
    Last edited by a moderator: Apr 8, 2013
  16. DavidC

    Regular

    Joined:
    Sep 26, 2006
    Messages:
    347
    Likes Received:
    24
  17. iMacmatician

    Regular

    Joined:
    Jul 24, 2010
    Messages:
    773
    Likes Received:
    200
    It apparently also has 8 GB of 5.5 Gbps memory with a 512-bit bus, plus a 300 W TDP.
     
  18. LiXiangyang

    Newcomer

    Joined:
    Mar 4, 2013
    Messages:
    81
    Likes Received:
    47
    Just returned from the IDC, according to the intel guys:

    1)The LLC cache arrangement of Phi is not like these found in intel CPU, LLC(which is L2 for phi) of Xeon Phi is local to each core, so for each core there is only 512kB L2 cache, instead of the 31MB number Intel promoted, any data cached that need to be accessed, that not avilable at the local L2 cache, will need to be transfered to the local L2 before accessing.

    For comparison, GK110 has 1.5MB of L2 cache, but it is global cache like Intel's LLC on ivy bridge/sandy bridge CPUs, so its data is accessable to all gpu cores.

    2)At least according to the intel guys at IDC, Intel has no plan to introduce programmable L1 cache into their future generation MIC co-processors.

    3)Xeon Phi's SIMD unit is more or less the same as Haswell's AVX-2, just wider.

    4)Unlike HT in CPU, hardware multi-threading on MIC is estenial for MIC to achieve peak performance.

    5)Intel's guys here are very open to promote MIC's programmability comparing to Nvidia's offers, but remain tight-lipped regarding the performance comparison between the two products.

    6) The card is likely to be cheaper than K20/K20X, but it is not for retail, only provided with whole system solution, and some company at IDC manage to pack 4 of these cards in one case with dual socket CPUs.
     
  19. moozoo

    Newcomer

    Joined:
    Jul 23, 2010
    Messages:
    109
    Likes Received:
    1
  20. mczak

    Veteran

    Joined:
    Oct 24, 2002
    Messages:
    3,015
    Likes Received:
    112
Loading...

Share This Page

  • About Us

    Beyond3D has been around for over a decade and prides itself on being the best place on the web for in-depth, technically-driven discussion and analysis of 3D graphics hardware. If you love pixels and transistors, you've come to the right place!

    Beyond3D is proudly published by GPU Tools Ltd.
Loading...