AMD RDNA4 Architecture Speculation

The L3 latency got a sizable hit due to the chiplet approach. Bandwidth went up at least.
Assuming the plan is still to have the L3 off die in future, I wonder how much it would help if they bump the L2 up to 2-4MB per SE to try and compensate.
 
Assuming the plan is still to have the L3 off die in future, I wonder how much it would help if they bump the L2 up to 2-4MB per SE to try and compensate.

Given how well stacking works on the Zen side, I feel like the plan in the future is to put the L3 (and memory controllers) on a base die, as they are on MI300. The hybrid bonding process is not horribly expensive, and gets them a much lower latency and higher bandwidth link than anything else.
 
Given how well stacking works on the Zen side, I feel like the plan in the future is to put the L3 (and memory controllers) on a base die, as they are on MI300. The hybrid bonding process is not horribly expensive, and gets them a much lower latency and higher bandwidth link than anything else.

Especially now that they've put the cache on ryzen 9000 series underneath the cpu cores. If they can package it so the cache is underneath the gpu cores you don't have to worry as much about the cache getting cooked.
 
Especially now that they've put the cache on ryzen 9000 series underneath the cpu cores. If they can package it so the cache is underneath the gpu cores you don't have to worry as much about the cache getting cooked.
Even if they will stick to a single Compute die, wonder if they would be able to like stack the memory die in an underneath cache die? Minimise the amount of unshrinkable silicone on the precious Compute die.
 
they're doing literally just that for Venice so yea.
I mean since I can't edit just to clarify like the memory bit bus because especially for large memory bit bus (i.e. 512-bit bus), that's a lot of precious space.

Though one use I could see that working in favour could be next gen consoles; have a cheap-ish TSMC N6 Memory-bit Bus/IOD/Cache die stacked underneath a potent more fancy Compute die with whatever the best stuff can be fit (if 2028/2029 that could mean a TSMC A16P Compute Die with UDNA Gen 2 & Zen 7)?
 
I mean since I can't edit just to clarify like the memory bit bus because especially for large memory bit bus (i.e. 512-bit bus), that's a lot of precious space.
512b is kinda pointless if you're going for MALL in 3D.
Though one use I could see that working in favour could be next gen consoles; have a cheap-ish TSMC N6 Memory-bit Bus/IOD/Cache die stacked underneath a potent more fancy Compute die with whatever the best stuff can be fit (if 2028/2029 that could mean a TSMC A16P Compute Die with UDNA Gen 2 & Zen 7)?
ah no SoIC-X cost structure makes it out of question for consoles.
It's strictly a premium thing.
 
RX 9070 XT 32GB SKU rumored

It is claimed that this might arrive as a gaming card (i.e. not a Radeon Pro) but the kind of task that stands to benefit most from the extra memory is likely AI.
I wouldn't be surprised if some gamers decide to hold out, though.
 
RX 9070 XT 32GB SKU rumored

It is claimed that this might arrive as a gaming card (i.e. not a Radeon Pro) but the kind of task that stands to benefit most from the extra memory is likely AI.
I wouldn't be surprised if some gamers decide to hold out, though.
Definitely thought it was about a W8700 but...
If they give it a ~450w TDP they could potentially push the N48 to ~5080 perf and with double the VRAM price it as a N31 replacement, $800-$1000.
 
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