Clock tree is another term for the integrated on-die network which distributes clock tics to the entire chip. The "trunk" of the tree starts at the clock generator, which is onboard the CPU itself. The "limbs" and "branches" of the tree speak to how those clock signals are distributed around the die. It's more a tree in logical representation than physical layout, of course.
They weren't very specific about how the clock tree plays into the vMin conversation. One interpretation might be the clock tree network itself is somehow damaged by voltage (it's made of silicon transistors like everything else in the die) and somehow this physical damage results in missing or otherwise skewed / corrupted clock signals being transmitted. If the discrete components of a CPU get out of lock-step with eachother, everything immediately goes to hell. Think of latch and atomic operations where there are mandatory predecessor / successor steps for something to work, and then imagine when those get processed out of order. The user's perception of such a thing would be a hard lock, but it might come along with data corruption depending on what instructions were being processed when it stopped.
