The Intel Execution in [2024]

Why does anybody pay attention when any of these "news" outlets mention "yields". What yields? For which parts?

Intel has publicly mentioned that the D0 for 18A is under 0.4, and at that point it was like a year to mass production. For comparison for TSMC, D0 for N5 and N7 was ~0.3-0.35 at 3Q before mass production.

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Because they have no idea what they're talking about, like me! šŸ˜
 
A Korean outfit is reporting a 10% yield on 18A. Oof!

Woudn't we have to know what they're trying to make with it for this to be meaningful? Like 10% of what?

Otherwise I think we'd just need to now how many defects there are on a wafer and maybe how they are distributed. Someone who knows please correct me if I'm wrong. This is interesting to me.
 
To some degree it does depend on what chip you're trying to lay down. At the same time, if there are enough defects that only 10% of (whatever you're making) comes out functional, then you have some problems..

Every new lithography process has issues; there were problems with 90nm just like 65nm just like 45nm just like 32nm et al. At eighteen angstroms (ignoring Intel's marchitecture name for what mostly isn't actually eighteen angstroms in any physical dimension) these transistors are effing tiny. A defect that could wipe out two or three whole transistors at 18A may not have affected a 14nm lithography node (following this new naming nomenclature, you could call it "140A") at all.

All that to say, it's only bad if they cannot fix it in a reasonable time. Newer, smaller lithography processes are insanely expensive, and this is one of the reasons why. While initial failure rates still may not be "unexpected", this is just really bad timing for Intel who is already struggling to demonstrate they aren't out of the fab business. I'm sure they were rushing the Broadcom business to secure a deal and the related finances; the rush probably made it worse. At some point, solving physics problems at this scale is simply time, and no amount of horse-whipping people with PhD's makes it go faster.
 
Woudn't we have to know what they're trying to make with it for this to be meaningful? Like 10% of what?

Otherwise I think we'd just need to now how many defects there are on a wafer and maybe how they are distributed. Someone who knows please correct me if I'm wrong. This is interesting to me.
It is BS.
 
At the same time, if there are enough defects that only 10% of (whatever you're making) comes out functional, then you have some problems..
That really depends on how hard it is to make. If you're making a 3,000 mmĀ² processor, you're never going to get great yields! And if you can sell those with insane margins, then it's not a business problem.

It is BS.
Please try again by actually explaining your POV. Start by at least saying which bit is 'BS'.
 
Please try again by actually explaining your POV. Start by at least saying which bit is 'BS'.
18A's D0 (defect density) was under 0.4 in September, around 3 quarters or more before it's supposed to start ramping to mass production.

That's similar to what TSMC has historically had.
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Well, hold on now, we can use a bit of critical thinking here. Nobody outside of a few specific people at Intel actually knows the true defect density of 18A. Intel has been very public in their search for 18A customers, and to have a big customer like Broadcom decide to cancel a deal shows that something isn't quite right. Do we know for certain it's because of defect rate? Nope. Do we know for certain it's NOT because of defect rate? Also nope.

I'd take "Intel says..." with a grain of salt, hopefully the same-sized grain of salt we all ingested when listening to what "Intel said..." about the 13th and 14th gen clocktree issues for months before they finally came clean.

Or did y'all forget that already?
 
Well, hold on now, we can use a bit of critical thinking here. Nobody outside of a few specific people at Intel actually knows the true defect density of 18A. Intel has been very public in their search for 18A customers, and to have a big customer like Broadcom decide to cancel a deal shows that something isn't quite right. Do we know for certain it's because of defect rate? Nope. Do we know for certain it's NOT because of defect rate? Also nope.

I'd take "Intel says..." with a grain of salt, hopefully the same-sized grain of salt we all ingested when listening to what "Intel said..." about the 13th and 14th gen clocktree issues for months before they finally came clean.

Or did y'all forget that already?
Noboby forgot, but you seem to be simplyfing the issue:
 
Well, hold on now, we can use a bit of critical thinking here. Nobody outside of a few specific people at Intel actually knows the true defect density of 18A. Intel has been very public in their search for 18A customers, and to have a big customer like Broadcom decide to cancel a deal shows that something isn't quite right. Do we know for certain it's because of defect rate? Nope. Do we know for certain it's NOT because of defect rate? Also nope.

I'd take "Intel says..." with a grain of salt, hopefully the same-sized grain of salt we all ingested when listening to what "Intel said..." about the 13th and 14th gen clocktree issues for months before they finally came clean.

Or did y'all forget that already?
No, but they said in front of their investors. You do realize how deep in s#%t they'd be directly lying to investors, right?
 
Lying is relative, and subjective, when dealing with corporate entities in which individuals cannot legally (in our current system) be held personally liable.
Noboby forgot, but you seem to be simplyfing the issue:
This was after how many months of denying there were problems? They only finally came out with the real story after literally months of being hounded by investigative journalists who were actually doing their job, versus "journalists" who were just parroting the bullshit Intel was putting out there. Intel outright denied any problems at all, blaming it on user voltage issues, and there is a SHITPILE of detail on this.

No, but they said in front of their investors. You do realize how deep in s#%t they'd be directly lying to investors, right?
"We took a sample wafer and the defect rate was (xxx). Therefore, we told our investor community the rate was 'healthy.' We have subsequently destroyed that sample wafer because it was no longer needed. We deny having any other irregularities with our lithography processes which were described to our investors at this particular date in question."

There, done. Now prove otherwise. /$100MillionUSDLawFirm

So what if someone finds out? Intel gets sued, maybe. The CEO is already out, and already got paid more than you and I combined, plus five orders of magnitude and absolutely no part of his very unlikely indictment and subsequent sentencing would be actual jail time. There's almost no limit to how low you're legally allowed to go when the only penalty is "fines" which are pennies on the massive payday dollar of a C-level executive at Intel.

Investers weren't to be worried about the clocktree issues, either.
 
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