If ATI/AMD GPUs are VLIW, what is NVIDIA's GPUs architecture acronym?

[Frontino]

We all know ATI/AMD use a VLIW architecture since R600, but I can't find anywhere what type of architecture is using NVIDIA since G80.
I know that G80 is a 16-way SIMD within an 8-way MIMD and that it's a superscalar architecture, but not a single word on the Internet of the exact acronym of the specific architecture type.

Anyone?

There's a list here, BTW

http://en.wikipedia.org/wiki/Instruction_set#Categories_of_ISA


Update of 31/01/2011:

Ok, so far I learned that G80 is a SIMD architecture and there is no MIMD at all, is that right?
But I'm not yet sure about how many SIMD arrays are there exactly. Shouldn't one of them be an entire cluster like the ones laser-cutted on the GF100 cards?
Anyway I posted a picture of the die along with a simple scheme of it and I'm actually seing 4 SIMD clusters.
In case I'm wrong, could any of you modify the die shot to draw the actual SIMD units?

G80 die shot:

G80 die scheme:

Here is a GT200 die shot with schematics:

And GF100 die shot:

 

[Sound_Card]

ATi has used VLIW since R300 actually.

 

[Alexko]

In current NVIDIA GPUs, SMs feature SIMT units: Single Instruction, Multiple Threads.

 

[3dilettante]

If the threads in execution were able to be transparently run on the physical SIMD units with no restrictions beyond performance, it would be something like SIMT.
There are certain areas where the architecture cannot hide the SIMD implementation, such synchronization with divergent control flow. If the lanes cannot always behave like threads, it is more appropriate to consider Nvidia's architecture to be SIMD if you aren't in their marketing department.

 

[Psycho]

..and there no differentiation to AMD's architecture there, at those upper SIMD/MIMD levels.
I would just call NVIDIA's SMs scalar at the level where AMD's are VLIW.

But was R300-R500 really VLIW and not just vector? Maybe they had the dot product but otherwise I thought it was same instruction for all 4 lanes.

 

[trinibwoy]

Weren't NV4 and G7x VLIW as well? Is the difference between that and vector simply that with vector all lanes must run the same instruction?

But yeah at the processor level current architectures from both sides are equally SIMD. The real differences are in instruction scheduling and ALU configuration.

 

[Dave Baumann]

1516954But was R300-R500 really VLIW and not just vector? Maybe they had the dot product but otherwise I thought it was same instruction for all 4 lanes.

R3xx-R4xx was 3+1 (co-issue and dual issue) and R500 was 4+1, so they were but more limited.

 

[pcchen]

If the threads in execution were able to be transparently run on the physical SIMD units with no restrictions beyond performance, it would be something like SIMT.
There are certain areas where the architecture cannot hide the SIMD implementation, such synchronization with divergent control flow. If the lanes cannot always behave like threads, it is more appropriate to consider Nvidia's architecture to be SIMD if you aren't in their marketing department.

I think it's more appropriate to say that it's SIMD with multi-threading support.

 

[Arnold Beckenbauer]

R3xx-R4xx was 3+1 (co-issue and dual issue) and R500 was 4+1, so they were but more limited.

Do you mean Xenos/C1 with R500?
Because R520 is 4+1 for VS and 3+1 for PS.

 

[Frontino]

But aren't NVIDIA GPUs many SIMD within many MIMD? And aren't those just classes of architecture of Flynn's taxonomy?

http://en.wikipedia.org/wiki/Instruction_set#External_links

At the bottom of that page I linked there is a list of architectures:

CISC
EDGE
EPIC
MISC
OISC
RISC
VLIW
NISC
ZISC

For example, in the RISC category fall the Cell B.E. and ARM processors.
In the VLIW category fall ATI/AMD GPUs and the Itanium processors.
So, where does NVIDIA GPUs stand?
Maybe CISC?

 

[pcchen]

Since NVIDIA doesn't release its internal instruction sets of their GPUs to public (the PTX is only an intermediate format), it's hard to say that whether they are CISC or RISC. However, there is no apparent advantage for them to have CISC instruction sets.

 

[Alexko]

If the threads in execution were able to be transparently run on the physical SIMD units with no restrictions beyond performance, it would be something like SIMT.
There are certain areas where the architecture cannot hide the SIMD implementation, such synchronization with divergent control flow. If the lanes cannot always behave like threads, it is more appropriate to consider Nvidia's architecture to be SIMD if you aren't in their marketing department.

Their marketing department calls it scalar…

 

[Frontino]

I made further research and it seems to me that R600 and G80 are both MIMD architectures:

R600 is a MIMD architecture of 4 SIMD clusters of 16 VLIW5 ALUs.
G80 is a MIMD architecture of 16 SIMD clusters of 8 scalar ALUs.

Am I correct?

 

[Frontino]

And GF100 should be a MIMD architecture of 32 SIMD clusters of 32 scalar ALUs, right?

And if R600 is a VLIW ISA, could G80 be a RISC ISA?

 

[Simon F]

But aren't NVIDIA GPUs many SIMD within many MIMD? And aren't those just classes of architecture of Flynn's taxonomy?

http://en.wikipedia.org/wiki/Instruction_set#External_links

At the bottom of that page I linked there is a list of architectures:

CISC
EDGE
EPIC
MISC
OISC
RISC
VLIW
NISC
ZISC

I expect you'd enjoy Beyond the valley of the lost processors

 

[mczak]

And GF100 should be a MIMD architecture of 32 SIMD clusters of 32 scalar ALUs, right?

GF100 is only 16 SIMD clusters...
But otherwise, isn't that more like multicore of simd clusters?

And if R600 is a VLIW ISA, could G80 be a RISC ISA?

I guess so.

 

[3dilettante]

One of the press pieces released by Nvidia indicated that Fermi revamped the internal ISA to make it more like a load-store architecture, which would make it closer to a RISC than it was on G80.
G80 apparently had reg/mem instructions, which is closer to CISC than RISC.

 

[rpg.314]

And if R600 is a VLIW ISA, could G80 be a RISC ISA?

VLIW and RISC describe different things and hence aren't mutually exclusive. IN fact, VLIWs (Itanium for instance) tend to be RISCish.

 

[rpg.314]

I expect you'd enjoy Beyond the valley of the lost processors

Great read. :smile:

 

[Gubbi]

G80 apparently had reg/mem instructions, which is closer to CISC than RISC.

I'm guessing the register file, being just a fast chunk of SRAM, was addressed using regular memory addresses. That is the register file really existed in regular memory space (similar to zero page memory of good ol' 6502).

Cheers