It's been well documented that ATI's and Microsoft's decision to incorporate eDram in the Xenos design, and the tiling requirement that results from it, has a number of trade-offs. Seemingly one of the key elements of the eDram design is to support 4xMSAA with no fillrate or bandwidth penalty. But due to the frame buffer size restraints and the tiling required to reach HD resolutions, are the additional sample units and bandwidth going to be unused. Can anyone propose work arounds, correct, or clarify any of the following.
1) Effective tiling requires engine modifications to support it as well as changes in the art pipeline wtr to how geometry might typically be batched and submited.
2) "Z only prepass can't fit at 720p w/ 4xAA". I don't understand why Dave says a geometry pass would be the performance path independent of tiling. It seems to me that the results of the pre-pass would be discarded sans for the information stored in the Hi-Z buffer, which according to Fran is also not sufficiently large to hold 720p @ 4xAA. (which I don't understand either, is it even true, and if so, why doesn't the resolution of the Hi-Z just become coarser?) The idea of a pre-pass in a traditional architecture would be to save bandwidth on overdraw, but doesn't the eDram alone already negate that benefit? How might this limitation be overcome?
3) "XPS is not compatible with tiling." Why is this? I can envision scenarios in which it should still work and others in which it wouldn't. Is there a general problem in doing this or does it depend on the application.
1) Effective tiling requires engine modifications to support it as well as changes in the art pipeline wtr to how geometry might typically be batched and submited.
2) "Z only prepass can't fit at 720p w/ 4xAA". I don't understand why Dave says a geometry pass would be the performance path independent of tiling. It seems to me that the results of the pre-pass would be discarded sans for the information stored in the Hi-Z buffer, which according to Fran is also not sufficiently large to hold 720p @ 4xAA. (which I don't understand either, is it even true, and if so, why doesn't the resolution of the Hi-Z just become coarser?) The idea of a pre-pass in a traditional architecture would be to save bandwidth on overdraw, but doesn't the eDram alone already negate that benefit? How might this limitation be overcome?
3) "XPS is not compatible with tiling." Why is this? I can envision scenarios in which it should still work and others in which it wouldn't. Is there a general problem in doing this or does it depend on the application.
