Xenos and R520/R580 - Design Differences

Discussion in 'Architecture and Products' started by Luminescent, Oct 19, 2005.

  1. Luminescent

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    The overarching design goal that permeates both architectures, Xenos and R520/R580 alike, is that of dynamically maximizing available resources according to processing load. Both architectures have been prepared to realize what I call "dynamic efficiency" in subtlely different ways.

    Since we're many of you are familiar with Xenos' and R520/R580's architectural configuration, I ask: how do the design protocols of each allow for "dynamic effieciency" and how do their approaches differ?

    Correct me if I'm wrong, but fundamentally, R580 and R520 offer a set of 8 MIMD vertex processors and 4 SIMD pixel processors operating independetly, in MIMD fashion, fed by a load balancing thread dispatch unit (scheduler). It offers a large register space to allow for many values for instructions that are in flight. I'm not sure whether the same scheduler feeds both the vertex and pixel pipes or whether there is a scheduler dedicated to each MIMD node, but if this is the case, R580 offers 4 scheduling/dispatch units for the pixel processors and 8 for the vertex processors (if each vertex unit operates as an independent unit). Within each SIMD pixel processor, R520/580 has 4 texture samplers and address processors available to it, although I'm not sure if they can operate independently of the ALU processors within the SIMD quad, with instructions issued to them independently in their own thread (although it would only be 1 thread for all four). In addition, R580 offers a ring bus and a programmable and dynamically adaptable memory controller with 32-bit granularity. The batch size allocated to each pixel thread in flight processors is relatively small, which I know affects the architectures ability to make efficient use of its units and handle dynamic branching.

    How does Xenos' processing configuration differ from the above? What are the ramifications Xenos' approach as opposed to R520/R580's?
     
    #1 Luminescent, Oct 19, 2005
    Last edited by a moderator: Oct 19, 2005
  2. Dave Baumann

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    Read the Xenos article.

    A few quick notes: VS in R5xx are not MIMD, they are still SIMD. Xenos doesn't feature the ring bus - its not big enough to really need it, was the reason give. Xenos's texture units will serve any of the 3 shader arrays.
     
  3. Luminescent

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    Can somebody verify whether the texture units operate independently of the ALUs (in their own thread) within a pixel quad unit?
     
  4. TurnDragoZeroV2G

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    Hijackin' this thread.

    Over in the console talk forum (probably wrong place, but I dislike creating redundant threads) I asked two questions regarding Xenos' capabilites versus R520/RV530, notably in dynamic branching (/flow control):

    http://www.beyond3d.com/forum/showthread.php?p=627543#post627543
    And
    Any explanation, links to sites/posts explaining, or guarantee the answer is somewhere in search wonderland (or worse, in the article :razz:, and in either case feel free to smack me) would be cool.
     
  5. Luminescent

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    I would also enjoy reading an answer to those questions, since I didn't understand some of those very aspects covered in the article.
     
  6. Luminescent

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  7. sireric

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    ALUs and texture operations are parallel, so independant. Well, as long as there is no dependancy :)

    Also, since there's heavy pipelining, talking about a "texture unit" is really talking about 100's of threads of work, being worked on, or waiting for their return data.
     
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