Xenon and Revolution CPUs: PowerPC 970 vs Power5 ?

[Megadrive1988]

okay we know Xenon (aka Xbox 2, aka Xbox Next) and Revolution (aka GCNext) are both going to be using IBM CPU processors based on either G5 / PowerPC 970 or perhaps Power5.

can someone explain all the differences between PowerPC 970 and Power5 ? ....besides the fact that one Power5 is a true duel core CPU, that can process 4 threads at once.

is there any advantage for Microsoft to use a Power5 CPU instead of a custom die with three PowerPC 970 based cores? I suppose one can argue that a triple PowerPC 970 CPU could process more threads (6) than a single Power5 (4 threads)..... I'm betting that a single Power5 has alot more cache than Microsoft's proposed triple core CPU (1 MB L2 in diagram), therefore the Power5 might be better balanced and better overall, perhaps?

 

[Guden Oden]

You can just forget the power5, it is a server-class chip that isn't meant to go into a console. Deadmeat was the fool who brought up that idea because he'd gotten into his head Microsoft in their drive to keep costs down didn't want a CPU with altivec instructions. That was his "evidence" to support that theory...

Since Power5 is a server chip it has oodles of cache, its power draw is likely too great for a console, and its die size definitely is beyond cost-effective limits.

"This is not the chip we're looking for. You may go about your business. Move along..."

 

[Brimstone]

If the CPU ends up with Vertex Shaders, to me it seems to be very difficult to compare the XB2 CPU to any traditional IBM PowerPC CPU. Dedicating transistors for graphic processing is something traditional IBM CPU designs don't do.

 

[Panajev2001a]

If the CPU ends up with Vertex Shaders, to me it seems to be very difficult to compare the XB2 CPU to any traditional IBM PowerPC CPU. Dedicating transistors for graphic processing is something traditional IBM CPU designs don't do.

The Altivec unit would run the Vertex Shader code.

 

[Wunderchu]

.... as I posted in this other thread (here: http://www.beyond3d.com/forum/viewtopic.php?t=9939&start=120 ):

I believe that the CPU of Xbox Next is a variant of the POWER5 processor , but there are 3 dual core chips [instead of 4 dual core chips, as in the server version of the processor ( http://www.beyond3d.com/forum/viewtopic.php?t=10182 )]....



although I do agree with Guden Oden, that the cache will definitely not be as large as in the POWER5 server CPU ;

Each IBM’s POWER5 chip contains two cores sharing 1.92MB of L2 cache and 36MB L3 cache. POWER5 typical processor is a 95mm x 95mm MCM with 4 chips (each chip contains 2 cores) feature astonishing 144MB of cache memory.

[source: http://www.xbitlabs.com/news/cpu/display/20031017104313.html ]

 

[Panajev2001a]

Wunderchu, each "physical" core in the POWER5 can act as two logical cores, so each of those POWER5 chips appears as 8 logical cores to the OS.

I think the XCPU2 will have three PPC970 cores modified to support SMT in each core.

 

[AlNom]

hokay..... lost me there at vertex shaderse on a CPU instead of on the VPU.....eh?!

 

[PC-Engine]

L2 cache is NOT expensive...trust me...at least not on cpus that are made using 90nm design rules and below...

 

[Farid]

L2 cache is NOT expensive...trust me...

You're right, 1.92MB of L2 cache won't indeed be a problem, this 36MB L3 cache will be, OTOH.
(if and only if Power5 were chooses as XCPU2... Which is not the case AFAIK)

 

[PC-Engine]

L2 cache is NOT expensive...trust me...

You're right, 1.92MB of L2 cache won't indeed be a problem, this 36MB L3 cache will be, OTOH.
(if and only if Power5 were chooses as XCPU2... Which is not the case AFAIK)

I'd say the L3 cache is just regular eDRAM.

 

[Brimstone]

hokay..... lost me there at vertex shaderse on a CPU instead of on the VPU.....eh?!

The VPU should end up with Vertex and Pixel shaders unified, with the CPU having Vertex shading also if a developer wants to use the CPU for that.

So if a developer wants to use all of the VPU's power for pixel shading they can do so and then have the CPU work on Vertex operations. But say the developer wants to have really complicated physics they can have the CPU's work on that and have the VPU work on Pixel Shading and Vertex Shading.

 

[Megadrive1988]

that's nice flexibility. kinda like having the best of both the Emotion Engine from PS2 and the Vertex Shaders from Xbox.

 

[Pepto-Bismol]

If Microsoft's next console is to have a lifespan beyond the present, then they will probably use a newer technology, like a variant of the nefarious Power 6.

Speaking of vector math, does this sound interesting to you guys?

Two Double-Precision Floating-Point Units
Two double-precision floating-point units provide the precision required for highly complex scientific computations. Although 32-bit processors are able to execute double-precision 64-bit calculations by cycling through the floating-point math unit multiple times, a double-precision math unit on a 64-bit processor can complete the same calculation in a single clock cycle. Two double- precision floating-point units let the G5 complete at least two 64-bit mathematical calculations per cycle.

Fused Multiply-Add
In fact, these floating-point units are also able to complete both a multiply operation and an add operation as part of the same machine instruction, thereby accelerating matrix multiplication and vector dot products. Either of the two floating-point units in the G5 can use a fused multiply-add instruction to complete the following computation in one pass:

T = (a * b) + c

On other processors, two instructions are required. The first is a multiply instruction. The product "U" would be used later by a second instruction, an addition, to complete the computation:

U = (a * b)
V = U + c

Thus, comparing processors with comparable clock speeds, the computation of "(a * b) + c " can be completed twice as fast by using fused multiply-add. What’s more, on the G5 round-off occurs just once in the computation of T, while on other processors, round-off occurs twice, both in the computation of U, and in the computation of V, so fused multiply add can deliver a more accurate result.

Source: Apple

 

[passerby]

Speaking of vector math, does this sound interesting to you guys?

Multiply/add has been around for a long, long, long time. I wouldn't be surprised if last generation's consoles have it(corrections welcome). Only funny thing is that it wasn't supported by Intel processors(*) - not sure about the P4 and more recent CPUs though.

(*) - Yes this is just Apple PR stuff - a dig at Intel of course.

In related news, Apple just debuted the latest top-of-the line G5 with dual PPC970 at 1.8Ghz, which needs liquid cooling, and admits that we wouldn't see PPC970 beyond 2GHz by this year.

Which means that the "3 CPUs at 3.5Ghz in XBNext" is either one of the following:
1) BS
2) Very, very slimmed-down versions of PPC970/PPCwhatever.

 

[archie4oz]

In related news, Apple just debuted the latest top-of-the line G5 with dual PPC970 at 1.8Ghz, which needs liquid cooling, and admits that we wouldn't see PPC970 beyond 2GHz by this year.

I think you're in the wrong year... The 1.8 was a single proc model from last year... The 2.5GHz models just debuted (those are also using the 90nm 970FX) and those are the ones using liquid cooling. The rest of the lineup changed from single 1.8 and 1.6GHz models to dual 2GHz and dual 1.8GHz... The latter 2 models are still using the 130nm 970 (without the liquid cooling)...

Also it's unlikely any console would use a Power5... A derivative is more likely (remember the 970 is a derivative of the Power4)...

 

[Pepto-Bismol]

I think you're in the wrong year...

He's dead wrong actually. The (dual processor) PowerMac page is where I nabbed the quote!!

"The 2.5GHz model packs so much power into tight quarters that Apple designed a liquid cooling system, resulting in a cool tower that runs Photoshop nearly two times faster than a Pentium 4-based system." - Apple

Also it's unlikely any console would use a Power5... A derivative is more likely (remember the 970 is a derivative of the Power4)...

For obvious reasons, it cannot be the same chip. Otherwise an enterprising company who would normally purchase a $10,000 to $20,000 IBM server could spend $5,000 on consoles, kidnap a few graduate-level engineering students from the local university and jimmy-rig a more potent solution ... for a lot less.

 

[Guden Oden]

Speaking of vector math, does this sound interesting to you guys?

Double-precision (64-bit) math is nothing new. Heck, i387-compatible FPUs have been doing 80-bit math for a decade. Apple's bullshit is even thicker than usual if they're implying 32-bit (integer) chips can't do double precision floating-point calculations.

 

[archie4oz]

Apple's bullshit is even thicker than usual if they're implying 32-bit (integer) chips can't do double precision floating-point calculations.

This has nothing to do with precision or Apple bullshit, it's just Apple pointing out that PowerPCs have FMAC FPUs (which pretty much every other processor out there *except* x86 designs have)... And that is has symmetrical dual FPUs (which isn't a 100% accurate as only one of them supports FDIV IIRC) unlike x86 designs which spread functionality across multiple execution units, ergo giving the 970 more practical throughput on a larger variety of numerical problems...

 

[a688]

Speaking of vector math, does this sound interesting to you guys?

Double-precision (64-bit) math is nothing new. Heck, i387-compatible FPUs have been doing 80-bit math for a decade. Apple's bullshit is even thicker than usual if they're implying 32-bit (integer) chips can't do double precision floating-point calculations.

Apple never said that 32-bit chips COULDN'T do double percision, they said (according to that quote in the thread earlier) that it takes them MULTIPLE clock cycles to do the work.

 

[ERP]

Speaking of vector math, does this sound interesting to you guys?

Double-precision (64-bit) math is nothing new. Heck, i387-compatible FPUs have been doing 80-bit math for a decade. Apple's bullshit is even thicker than usual if they're implying 32-bit (integer) chips can't do double precision floating-point calculations.

Apple never said that 32-bit chips COULDN'T do double percision, they said (according to that quote in the thread earlier) that it takes them MULTIPLE clock cycles to do the work.

That's not actually true either......
I86 does every none SSE fp calculation at 80 bits, the only thing thaat takes longer is the load store. I also believe Power 4/5 use 128bit fp internally for none altivec operations.

Unless they're talking about a 64bit altivec, I'm missing the point.