Yeah, I suppose you're right there. I was kind of just throwing an idea there with OOOE, but after thinking about it (and after some sleep!), it would make sense to just add more cores with a healthy increase in clockspeed. Supposing they start out at 32nm in 5 years time, they should be able to fit 8 times the number of transistors on-die than on 90nm. As per your suggestion, they can triple the number of cores or even quadruple it. Perhaps they should work on adding in "true" dual threads to avoid context switching? I'm not sure what the transistor cost of that would be. The rest of the space could then be taken up by a massive L2 cache.
In the
die-shot of Waternoose, it looks like the 1MB L2 takes up about the same area as a single core (I'm not too clear on this, but it looks like they have it in 256kB chunks). With 12 cores @32nm, that's still half the area of 90nm three-core with which to play. They could then add up to 16MB of L2 (20MB total) to take up the remainder of the space (I assume linear space-consumption so that 1MB == area of 1 core as per the picture). That can be roughly split into just over 1.66MB per core... which I take it should be decent
This also assumes they make no changes to the cores at all. So scale back to 1MB per core, giving enough space approximately equal to 8 cores; allow for some changes to the 12 cores. I'm not too sure what would take 67% more die area, perhaps the transistors needed for two separate threads to exist simultaneously (to avoid context switching?). Someone please correct me on that!
At 32nm, I'd like to see what they'll pack into GPUs
