We've had some discussion on 'Flipchip Packaging' and how that differs to Wirebond packaging, but you may not have seen what Wirebond pacaking actually means as they are ususally encased in a ceramic coating.<p align="center">Click Image To Enlarge
</p>The image above is actually an A1 test revision of NV18. Test revisions such as these are not in ceramic coating, but have a rubber shim so that its easy to do the necessary silicon verification on the chips.
You can see that a wirebond package literally has wire traces from the edge of the chip out to the substrate to connect to the pins in the bottom of the package.
</p>The image above is actually an A1 test revision of NV18. Test revisions such as these are not in ceramic coating, but have a rubber shim so that its easy to do the necessary silicon verification on the chips.You can see that a wirebond package literally has wire traces from the edge of the chip out to the substrate to connect to the pins in the bottom of the package.
