Will L2 cache on X360's CPU be a major hurdle?
- Thread starter Korrupt
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SPEs have 256KB of local store and no cache. CELL PPE has 512KB L2 cache and (I assume) 64KB L1.
Xenon has 1MB of shared L2 cache between 3 cores which each have 64KB L1 cache.
At least that is how I remember each design. (I am sure Shifty can correct me if I am wrong).
Will cache be an issue next gen? Of course, every limitation is an issue.
But as noted by others in the past, 3D games tend to use less cache (partly because there is a lot of streaming). A shared cache has some advantages like easy sharing between processors. Another nice thing about 1 big cache is that a large chunk of code can fit into it. Numerous small caches could run into issues where you have 1 large program and 4 or 5 small ones. The small ones are no problem in either design, but if you have a large chunk of code, lets say 600KB large, it wont fit into a smaller segmented cache. So in that case a large 1MB cache shared is better than 3 smaller caches.
In general cache will be an issue in the 360. It will be something developers keep in mind when designing their engines and in some cases will just need to design around.
Ditto the SPEs. Design to its strengths while minimizing any limitations.
Another benefit mentioned in regards to separate caches is it could minimize the effects of thrashing on the other cores.
Xenon has 1MB of shared L2 cache between 3 cores which each have 64KB L1 cache.
At least that is how I remember each design. (I am sure Shifty can correct me if I am wrong).
Will cache be an issue next gen? Of course, every limitation is an issue.
But as noted by others in the past, 3D games tend to use less cache (partly because there is a lot of streaming). A shared cache has some advantages like easy sharing between processors. Another nice thing about 1 big cache is that a large chunk of code can fit into it. Numerous small caches could run into issues where you have 1 large program and 4 or 5 small ones. The small ones are no problem in either design, but if you have a large chunk of code, lets say 600KB large, it wont fit into a smaller segmented cache. So in that case a large 1MB cache shared is better than 3 smaller caches.
In general cache will be an issue in the 360. It will be something developers keep in mind when designing their engines and in some cases will just need to design around.
Ditto the SPEs. Design to its strengths while minimizing any limitations.
Another benefit mentioned in regards to separate caches is it could minimize the effects of thrashing on the other cores.
cobragt said:
It's not a cache, but, like a cache, it is 0-wait state memory. Cell has 256*7 + 64 = 1856 kB of 0-wait state memory, and 512kB of small-wait state memory (PPE's L2). Xenon has 64*3 = 192kB of 0-wait state memory, and 1MB of small-wait state memory. It's largely anyone's guess as to how these numbers actually affect realworld performance at this point.
mckmas8808
Legend
What's so good about 0 wait-state memory?
inefficient
Veteran
PC-Engine said:
"through the cache" you say that as if that were a bad thing
And you can just lock the L2 cache if you want to actually just bypass it.
L1 and L2 cache are highly automated memory systems, which makes them simple to program for.
The only difference between L1 and L2 cache and the memory found on each SPE is that developers can dictate the way they wish the memory to be used on each SPE, increasing efficiency, however it operates much in the same manner as a cache would, that's why the local memories aren't traditonal cache.
The only difference between L1 and L2 cache and the memory found on each SPE is that developers can dictate the way they wish the memory to be used on each SPE, increasing efficiency, however it operates much in the same manner as a cache would, that's why the local memories aren't traditonal cache.
inefficient said:PC-Engine said:
"through the cache" you say that as if that were a bad thing
And you can just lock the L2 cache if you want to actually just bypass it.
The point I'm making is that how can LS function as cache if it doesn't have a direct connection to main RAM? If it can function as cache then why does it need to connect to another pool of cache to get to main RAM? AFAIR LS can't bypass the 512kb and go straight to RAM. Isn't the point of cache to cache data from main RAM so that you don't have to go offchip since it's a lot slower? If LS doesn't have a direct path to main RAM then how can it fill its LS and operate as cache? In essence the 7 SPEs will be fighting with the PPE over the 512kb of actual cache.
AlgebraicRing
Newcomer
Can we get back to the topic at hand? I think the thread starter is asking whether or not it was a design mistake to have a shared cache for the three processors. Particularly I would like to know if there is a way to partition the cache so that each processor can get a specified chunk of cache space. If there is no way to partition the cache, then is there a way to prevent one processor from filling the cache with its pages of memory which then push the pages of memory out which belong to the other two processors?
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