What is the true spec of PSX3 CELL???

[DeadmeatGA]

You heard the CELL numbers from various sources, 4 cores on a chip, 4 Ghz, 1 Teraflops/s. Somehow, I don't buy any of these numbers because they don't add up. Please allow me to dissect these numbers...

1. 4 CELL cores on a chip.

4 CELL cores??? For real? EE VUs took up 5.5 million transistors and CELL VUs are bound to more than double those numbers, because of various enhancements and 128 KB cache(Assuming this is an eDRAM based cache and not a SRAM circuit). At more than 6 million transistors per VU, you are looking at a figure of 60~70 million transistors per CELL core. Such core is fabricable as single chip, but to put 4 of them into single chip is rather problematic. Even the latest unified PSX2 ASIC containing 55 million transistors and fabricated on same 0.09 micron process measures 88 mm2 large.

This is why I suspect that PSX3 CELL will contain dual core instead of rumored four.

2. 4 Ghz Clockspeed.

4 Ghz?? PowerPC never clocked this high, not even the latest Power4 doesn't clock this high. 2 Ghz is more realistic.

3. 1 Teraflops/s

Let's do the revised math again. 16 VUs x 8 FLOPS x 2 Ghz = 256 GFLOPS.

We will see who is right two years from now, SCEI marketting man's 1 Teraflops Vs DM's 0.25 Teraflops...

 

[Megadrive1988]

.
.
Deadmeat - there are some reports that PS3 version of Cell will have 8 or even 16 cores - remember, 4 cores was the low-end figure for less complex chips.

The article from Mercury News reports that PS3's CPU will have
72 processors, consisting of 8 PowerPC cores and 64 APUs.
thus, 8 "Cells" or Processing Elements.

http://www.bayarea.com/mld/mercurynews/5311288.htm

With the PS 3, Sony will apparently put 72 processors on a single chip: eight PowerPC microprocessors, each of which controls eight auxiliary processors.

Using sophisticated software to manage the workload, the PowerPC processors will divide complicated problems into smaller tasks and tap as many of the auxiliary processors as necessary to tackle them.

 

[V3]

4 CELL cores??? For real? EE VUs took up 5.5 million transistors and CELL VUs are bound to more than double those numbers, because of various enhancements and 128 KB cache(Assuming this is an eDRAM based cache and not a SRAM circuit). At more than 6 million transistors per VU, you are looking at a figure of 60~70 million transistors per CELL core. Such core is fabricable as single chip, but to put 4 of them into single chip is rather problematic. Even the latest unified PSX2 ASIC containing 55 million transistors and fabricated on same 0.09 micron process measures 88 mm2 large.

Well EE and GS is over 200 mm2 at first. They are also aiming for 65nm process.

4 Ghz?? PowerPC never clocked this high, not even the latest Power4 doesn't clock this high. 2 Ghz is more realistic.

Nope, only those APUs are supposedly clock that high. The core, have no idea at this moment.

 

[Paul]

This guy needs to be banned.

 

[Paul]

1. 4 CELL cores on a chip.

That's what Broadband engine is, 4 PE's stuck together.

CELL cores??? For real? EE VUs took up 5.5 million transistors and CELL VUs are bound to more than double those numbers

Your point?

Such core is fabricable as single chip, but to put 4 of them into single chip is rather problematic.

How so?

At more than 6 million transistors per VU, you are looking at a figure of 60~70 million transistors per CELL core.

We are looking at PS3 having atleast a billion transistors total.

Even the latest unified PSX2 ASIC containing 55 million transistors and fabricated on same 0.09 micron process measures 88 mm2 large.

Sony and Toshiba are mass producing Cell at 65 nm.

4 Ghz?? PowerPC never clocked this high, not even the latest Power4 doesn't clock this high. 2 Ghz is more realistic.

Your talking about a god damn chip that will be in products 2005.

We will see who is right two years from now, SCEI marketting man's 1 Teraflops Vs DM's 0.25 Teraflops...

My guess is that your going to be eating your words, But I guess you'll bail out of here once we know some hard specs come March.

 

[DeadmeatGA]

...

Deadmeat - there are some reports that PS3 version of Cell will have 8 or even 16 cores.

On multichip configuration, yes. On a single chip configuration, nope.

Well EE and GS is over 200 mm2 at first. They are also aiming for 65nm process.

Well, have two CELL cores on a chip and you are already approaching 200 mm2. Does Sony intend to release the first gen PSX3 units as a multichip system then integrate later?? Because it is clearly unfeasible to pack all four cores into single die on 0.09 micron process.

 

[Paul]

Cell isn't getting mass produced on 0.09 micron Deadmeat...

It's getting mass produced in the Toshiba Oita plant 2004 at 65 nm.. Than the new Sony 65 nm fabs will kick in 2005.

 

[cthellis42]

!!......!!!!!!.....but Paul, it is clearly unfeezable to put those chip things out on 90nm!!!...!!111!

 

[Paul]

OMGHI2U SONY IS LIKE STUPID CUZ U KNOW cell?? i kno my friend tell me it be failure cuz it's liek too big u know to fit on the c hip right

so i ask him y and he say it because i touch myself at night!!! OMG Y HELO THAR BUTTSECKZ LOL LOL

 

[jvd]

This guy needs to be banned.

People have said the same about u .



To answer his question though . The cell chip is scalable . Which one ends up in the ps3 is anyones guess. Most likely the 16 "cores" Mabye less mabye more . Depends on what else is coming out . How expensive it is to make , yields , and i guess other factors

 

[Megadrive1988]

At more than 6 million transistors per VU, you are looking at a figure of 60~70 million transistors per CELL core.

But Deadmeat, we have statements from 1999 by Sony, printed Next Generation magazine and EETimes (as well as other places) stating that Playstation 3 will have Emotion Engine 3 with over 500 million transistors. And by now, that figure could have increased by 2~3 hundred million, bringing the CPU alone to 500~800M transistors.

I dont see why we cant have 36~72 processors on a single chip.
(4 PPC cores plus 32 APUs or 8 PPC cores plus 64 APUs) as well as eDRAM.

 

[Grall]

Re: ...

Because it is clearly unfeasible to pack all four cores into single die on 0.09 micron process.

How would YOU know anyway? You're neither a programmer, nor a CMOS engineer!

You're a classic internet FUD-troll, dead. You construct a false scenario of your own (Cell on .09, despite you KNOW they're aiming at .065, that's been common knowledge a long time now), and then come up with equally made-up arguments to despute your own scenario. That's criminal behavior in a serious forum IMO, and you need to be removed.

Forcefully, if neccessary.

*G*

 

[DeadmeatGA]

...

To Jvd

The cell chip is scalable

Everyone knows that. But my question is, can you fit all of them on a signle die???

To Megadrive

I dont see why we cant have 36~72 processors on a single chip.
(4 PPC cores plus 32 APUs or 8 PPC cores plus 64 APUs) as well as eDRAM.

Because you don't have an unlimited transistor budget.

To Grail

How would YOU know anyway? You're neither a programmer, nor a CMOS engineer!

You learn.

You construct a false scenario of your own (Cell on .09, despite you KNOW they're aiming at .065, that's been common knowledge a long time now)

Who says the switch to 0.065 micron will be smooth and trouble free??? Since Sony is the first one to adapt 0.065 micron, they will be the first to encounter all the problems of fab switch.

you need to be removed.

Unlikely. Trolls launching personal insults against other have gone unpunished. I do not insult others, only present compelling cases.

 

[Vince]

Re: ...

Unlikely. Trolls launching personal insults against other have gone unpunished. I do not insult others, only present compelling cases.

Hardly. You have actually compelled me to post. Congradulations. Intel has anticicapted a Billion+ transistor IC based on the 65nm process with 16MB of L2 running at 6GHz. This has been stated multiple times by Intel fellows, most recently I've seen it in a presentation on petaFlop clusters in the 2009/2010 timeframe.

You have not learned enough.

 

[DeadmeatGA]

...

Intel has anticicapted a Billion+ transistor IC based on the 65nm process with 16MB of L2 running at 6GHz.

Two problems with this.

1. Intel's device is not due until 2007.
2. Intel's device has only 140 million logic transistors. The rest are SRAMs.
3. Even Madison with 500 million transistors is unable to fit more than one core.

 

[Vince]

Re: ...

1. Intel's device is not due until 2007.
2. Intel's device has only 140 million logic transistors. The rest are SRAMs.
3. Even Madison with 500 million transistors is unable to fit more than one core.

• Time is irrelevent, only process technology
• Ok, then go with Power4's 170M at 180nm, regardless of the logic count, the vastly inferior process technology makes up for it
• Again this isn't valid, for several outstanding economic reasons based on Intel's market.

http://www.eedesign.com/columns/tool_talk/OEG20030616S0058[/url]]The core issue is that 90-nanometer ICs can contain 100 million gates

http://www.eetimes.com/in_focus/silicon_engineering/OEG20021219S0031[/url]]Ninety-nanometer process technology enables the creation of chips with 175-million gates aboard a single die

As this article states, the first will be an IC delived for graphic design, not bulk. STI's Cell could very well be close based on historical precedence. http://www.reed-electronics.com/semiconductor/index.asp?layout=article&articleid=CA279104

 

[cthellis42]

Re: ...

Who says the switch to 0.065 micron will be smooth and trouble free??? Since Sony is the first one to adapt 0.065 micron, they will be the first to encounter all the problems of fab switch.

I don't think any of us have EVER claimed that 65nm would be trouble-free, but they have been aiming for it for a while and building entirely new fabs for this purpose, and investing billions aimed strictly for this purpose... Realisticly, it would seem all three believe it can be brought to bear, and are investing heavily on every level to ensure the smoothest run-out as possible.

However, that you are skeptical does not dictate that Sony will be using a 90nm process, so it would be nice if you removed that from the majority of your complaints so far.

 

[DeadmeatGA]

...

Time is irrelevent, only process technology

Actually time is relevant, Sony can't be doing things alone that Intel and IBM can't.

Ok, then go with Power4's 170M at 180nm, regardless of the logic count, the vastly inferior process technology makes up for it

Well, a 400 mm2 die isn't exactly for a consumer application...

Let's assess what is possible in 2005 time frame; 0.09 micron? Yes. 0.065 micro? Too optimistic. 100 million SRAM gates? Yes 100 million logic gates? Hell no. How the hell are you supposed to fit 4 PPC cores, 32 VU2s, and 1 MB of cache(be it SRAM based or eDRAM based) into single die in 2005????

 

[cthellis42]

Even just according to Moore's law, the process and talking about billion+ transistor chips would normally be expected by 2007. Thankfully Moore's law is not and companies with the time and talent and cashola attempt to break it as much as they can. It's been broken before, and will be again.

How successful will they BE? Who the hell knows? But IBM certainly isn't well-known for pushing things they cannot possibly do out the door. (Nor are too many companies that remain--well--big companies.) And what will it all MEAN? That we also cannot answer. They may not be able to time all the hardware and software and toolsets and all other support channels to an amazing degree in their proposed launch window, which means they may slip some or we may get the same PS2-scale ramp-up. (Which if you notice didn't stop the PS2 at all, gave it impressive gains even within just a year's time, and continues to stretch now, just over halfway through its lifespan.)

No one can, of course, know, and certainly not you. Myself, I lean a little more in the direction of hundreds (over a thousand?) engineers and billions of dollars.

 

[PiNkY]

btw, Moore's so called law states that on avg. ic complexeties double every 18 months. We've had consumer level ic's with 100 Mio + transistors readily available mid 2002. So by that measure 400-500m transistor chips by mid 2005 would be supported by that model and processors like Intel's Madison, Prescott and perhaps even PS2's R5900 are quite a bit more complex (brainaic) then PS3's PEs and (certainly) its VUs will probably end up being, so IMHO most of your arithmetic is quite pointless.