Wafer Production..

[Hellbinder]

Would one or more of you comment on the actual process of "burning" or creating a wafer? how its done?

Also how long does it take to actually produce a wafer from the time the laser hits it the first time.

Is there somewhere you can go to see this process? a Demo or a Video or something?

 

[bloodbob]

Ehh I the only thing I think they use a laser for would be to slice the semiconductor crystal.

http://www.tocera.co.jp/en/products/wafer/process.html

 

[Geeforcer]

No, they use a diamond-edge blade for that.

 

[Lazy8s]

Besides etching, wafers cycle through several different production processes throughout a week or two stay at the fab. They're baked in big ovens and exposed to UV radiation during the diffusion stage, they're bombarded with recipes of potent gases and more radiation during implant, they go through acid exposure for the stripping stage, and they're continually sampled, tested, and retested during this time. A fab spends a great portion of its operation running pilot wafers and testing them to make sure that the machines are well caliberated and yeilding high rates of working product.

 

[KimB]

What has always amazed me about this is that the silicon is machined into these huge columns.

Each column is many feet in length (I forget how much, exactly, but the 60kg-100kg mass estimates on bloodbob's link should give you an idea: remember, silicon is going to weigh a similar amount to that of glass).

The crystal is grown in such a way that the entire column is one single crystal, and it must also be oriented in a specific way.

The machines then slice the silicon in incredibly thin sheets, and are cut so that a specific crystal surface is exposed.

I always thought that this part of the development, before any chips are even fabricated, was particularly impressive.

 

[Hellbinder]

Yeah, i had already read up on the actual single silicon cystal process. I am really wondering how they get the millions of mosfets, Jfets etc etc etc onto the wafer.

What process puts 300 million transistors onto a tiny square. is it laser etching? or wehat...

 

[{Sniping}Waste]

Yeah, i had already read up on the actual single silicon cystal process. I am really wondering how they get the millions of mosfets, Jfets etc etc etc onto the wafer.

What process puts 300 million transistors onto a tiny square. is it laser etching? or wehat...

I could post all you would like to know but that will end up a book.

 

[AlNom]

yeah it's pretty elaborate.. diagrams work best...

really really really really simply...

layer of chemical on top -> "chip" out the parts that will expose the area to create an n-or p-well (a few things going on here)-> do some dope... get rid of chemical layer...

start again...


there is some cheating with pmos/cmos part since we all have a giant P substrate with the nmos part already built...just make a large n-well inside the p-well...make two p-wells inside that n-well... and the nmos and pmos are now side by side.


here's a document that explains it actually...http://lsiwww.epfl.ch/LSI2001/teaching/webcourse/ch02/ch02.html

just imagine that everytime you want to make the well you have to cover the surface while you bombard the wafer.

 

[{Sniping}Waste]

yeah it's pretty elaborate.. diagrams work best...

really really really really simply...

layer of chemical on top -> "chip" out the parts that will expose the area to create an n-or p-well (a few things going on here)-> do some dope... get rid of chemical layer...

start again...


there is some cheating with pmos/cmos part since we all have a giant P substrate with the nmos part already built...just make a large n-well inside the p-well...make two p-wells inside that n-well... and the nmos and pmos are now side by side.


here's a document that explains it actually...http://lsiwww.epfl.ch/LSI2001/teaching/webcourse/ch02/ch02.html

just imagine that everytime you want to make the well you have to cover the surface while you bombard the wafer.

Who in there right mind uses nmos still. Nmos is power hungry and leaks heavly.

YOur link does a ggod job of showing what is done but not how its done. The how is what so huge I can't find a link that will some what show/tell how its done.

 

[AlNom]

no need to be sarcastic.

I believe Hellbinder said:

I am really wondering how they get the millions of mosfets, Jfets etc etc etc onto the wafer.

So why the ungrateful tone? Go write the book if you think my post was unhelpful in all ways oh knowledgable one.



write into discovery channel's "How stuff is made" or whatever if you want that info then. I'm sure they'll be able to give you a step by step guide on what buttons to push.


OH hey.... this is interesting... Intel describing nwells and pwells...p and n substrates...

http://www.intel.com/education/transworks/flat6.htm

You sure you're not talking about Pseudo nmos? You need nmos with pmos to make cmos.

 

[{Sniping}Waste]

no need to be sarcastic.

I believe Hellbinder said:

I am really wondering how they get the millions of mosfets, Jfets etc etc etc onto the wafer.

So why the ungrateful tone? Go write the book if you think my post was unhelpful in all ways oh knowledgable one.



write into discovery channel's "How stuff is made" or whatever if you want that info then. I'm sure they'll be able to give you a step by step guide on what buttons to push.


OH hey.... this is interesting... Intel describing nwells and pwells...p and n substrates...

http://www.intel.com/education/transworks/flat6.htm

You sure you're not talking about Pseudo nmos? You need nmos with pmos to make cmos.

Ok I see were your going with the nmos. Sorry I was thinging about the old day of Nmos before Cmos.

I did find some more info for all that want to spend some time learning semi fabing.
http://iisme.org/etp/Silicon_Wafer_Processing.pdf

Here is some more info.
http://www.semiconductor-manufacturing.net/Semiconductor-Industry-Overview.htm

 

[rwolf]

Actually I think they hire tiny gnomes with very small hammers.

 

[nelg]

http://www.intel.com/education/makingchips/index.htm

 

[aapo]

What has always amazed me about this is that the silicon is machined into these huge columns.

Yeah, the rotate-in-the-melt process is called Czochralski process after prof Jan Czochralski. Nowadays they may use VCz (vapour pressure controlled Czochralski) or some other exotic techniques, but I think the basic idea is indeed still the same.

Each column is many feet in length (I forget how much, exactly, but the 60kg-100kg mass estimates on bloodbob's link should give you an idea: remember, silicon is going to weigh a similar amount to that of glass).

I'd suppose the modern ingots are even bigger, but I don't really know. I've seen 4 inch wafer ingots that were couple of meters long, and I think I've still got some slices left from an excursion to a Finnish producer Okmetic.

The crystal is grown in such a way that the entire column is one single crystal, and it must also be oriented in a specific way.

The most astounding thing is that the wafer lattices nowadays usually contain not a single dislocation. The lattice itself is in a sense "perfect", even though there still exist some impurities.

The machines then slice the silicon in incredibly thin sheets, and are cut so that a specific crystal surface is exposed.

Well, they are usually 500 or 350 microns and either (001) or (111) surfaces. Some III/V material overgrowth techniques or micromechanics may require wafers with 0°-6° miscut angles, but these are not used in pure silicon processes.

I always thought that this part of the development, before any chips are even fabricated, was particularly impressive.

For sure. However, after a buffer layer growth the sample surface will get even better; if you take an AFM (atomic force microscope) micrograph of a particualrly good epitaxial surface, you'll see the individual atomic steps. The atomically planar surface is not possible even for a highly polished wafer surface without the buffer layer, which is the reason they use buffer layers in the first place.

 

[IgnorancePersonified]

I think I will stick to brewing my own beer.