Well, one question is, "Do ATI and NVidia use different design tools?"
They probably do. If you do a search for "ATI" and "Nvidia" at Cadence and Synopsys's website, you get some hits. Unfortunately, the scattered sketchy info doesn't prove ATI/Nvidia currently use different flows...only that future products are earmarked for certain design tools.
"Nvidia is known for its aggressive designs, but it is extremely weak in communicating its ideas to the foundries,"
I find this quote extremely ironic.
For one thing, as pure-play foundries, TSMC/UMC offer the least design-consulting services of all merchant foundries. There is no need for the fab-customer to interact with the foundry about his/her design (unless he wants some specific advice.) Customers simply download TSMC's design-kit and are expected to have the requisite CAD-tools and know-how to produce a GDSII file. The customer hands the foundry a GDSII file (electronic mask photograph), the foundry runs the design through an automated DRC (design rule check), then off it goes to the production floor. If the DRC fails, the foundry will notify the customer, who has the option to 'sign off' (i.e. approve production, accept all risks) or hold back.
Also, NVidia's new foundry partner, IBM, is well-known (among disgruntled ex-customers) for not communicating well, or not caring to communicate, with its ex-foundry customers. In fairness, IBM's three recent *major* design wins (NVidia, Xilinx, and one other company I can't think of) shows IBM's new dedication to the merchant-foundry business. In the past, every design had to move through IBM's internal P&R design services group, which customers affectionately called a 'black box', because no one knew what went on inside that group...the customer could only see the input and output.
IBM allowing external third-party CAD-tools handle back-end place&route/layout is a recent event. Here's an interview talking about the pluses and minuses of an internal tool flow
http://www.eedesign.com/features/exclusive/OEG20020122S0072. Ironically, as time goes on, NRE costs are skyrocketing for fabless companies. One way for customers to reduce the huge upfront dev cost is to handoff the backend work to the foundry. Customer pays a higher price/wafer, but the third-party back-end tools (like Cadence's SOC Encounter, Synopsys' Galaxy) are now well over $1.5M.
> The differences within TSMC for .13 microns for ATi and nVidia have been well documented by both companies for several months.
ATI and NVidia could be using different product-lines. TSMC offers several different foundry-products at the 0.13u node, and according to this article
http://www.eetimes.com/semi/news/OEG20030729S0018, yield varies quite a bit. There are many complex variables that go into final manufacturing yield. Some are controlled by the customer (# metal-layers, die-size, foundry recipe), some aren't (variability in the manufacturing line, accuracy of the development library, etc.)
After so many months of difficulty with TSMC, one certainly expects a customer (NVidia) to change the way it does things in order to accomodate previously unforeseen obstacles. Fixing 1 exotic design with another equally exotic design is just begging for a history-repeat lesson.
