Tiling
- Thread starter MistaPi
- Start date
I'm not sure exactly what that means, but I do know that Hyper-Z is a tile-based approach.
That doesn't mean that the Radeon cards are deferred renderers. A deferred renderer caches and sorts the entire scene.
The Radeon cards cache a little bit ahead, in order to improve the efficiency of their Hyper-Z technology. This is far from a perfect depth-sort, and it is doubtful that it is done on the full scene in most scenarios. Basically, ATI took the Radeon cards 30% of the way from an immediate-mode renderer to a TBR.
That doesn't mean that the Radeon cards are deferred renderers. A deferred renderer caches and sorts the entire scene.
The Radeon cards cache a little bit ahead, in order to improve the efficiency of their Hyper-Z technology. This is far from a perfect depth-sort, and it is doubtful that it is done on the full scene in most scenarios. Basically, ATI took the Radeon cards 30% of the way from an immediate-mode renderer to a TBR.
OpenGL guy
Veteran
All of the settings you have mentioned simply tell the driver how to arrange the data in memory. Many (all?) 3D architectures use tiled memory to take better advantage of memory bursts. All this means is that the arrangement of data in memory is better suited for things like bilinear filtering, etc.MistaPi said:
As far as I know the only thing this has to do with is the pattern of memory management used to access the textures, i.e., managing it in smaller blocks or larger chunks, across the AGP bus and maybe within the graphics card memory. But we could just wait for OpenGl guy's info. 
OpenGL guy
Veteran
Sort of.Chalnoth said:
Pretty much totally incorrect
Eh? It doesn't have any effects on the sort order - Radeons are still plain IMR's.
You can have more than one hierarchical z buffer. Normally you will have the ‘occlusion’ z buffer which stores the highest Z values; this will be optimal in front to back rendering. However, its also possible to have another storing the lowest Z values which can save on multiple Z reads in back to front ordering. I don’t know if ati actually do this (although someone one mentioned one of their patents references it and they actually got mixed up half way through the patent!).
OpenGL guy
Veteran
Because you don't know the hardware?Chalnoth said:OpenGL guy said:Pretty much totally incorrect
Why?
No. 3dcgi gave another possible answer.
It's a good technique
MistaPi said:
No, just has to do with optimised memory layout for caching. Textures are stored in a tiled way to optimised for the read pattern typical for rendering with bi- and trilinear filtering. To avoid huge texture caches the primary render surface is also access in a "tiled" way. Simple example say you stretch a 128x128 texture over a polygon, if you render the polygon in a line by line way then you'd have to cache all 128 texels of the texture to be able to have sensible re-use when you render the second line of the triangle, by splitting the framebuffer in tiles you reduce the amount of texels you need to maintain in the cache to have re-use over multiple lines. Obviously you still have potential cache misses along the tile borders.
All of this is very traditional and even the good'old trusty Voodoo1 did this. So nothing new or exciting, just memory data re-ordering and a classic non-linear buffer access pattern for improved efficiency.
Nothing to do with TBR even though this is again one of the many optimizations that tilers get "for free" as part of their rendering philosophy.
multigl2 said:
What is described can not even be called tile based rendering, since these architectures do not render tile by tiles. There is no sorting or bining in tiles for the principles mentioned above. Its just to improve memory access patterns. A Tile Based Memory Layout and access is not equal to tile based rendering and is not equal to deferred rendering. As long as there is no geometry sorting you can not call it tile based rendering since else a Voodoo1 was a tile based renderer.
K~
