mat said:
just out of curiosity: how expensive is it to produce/tape out a GPU? (just the producing... not the [more expensive?] R&D)
Depends on the size(.13u, .18u, .25u, etc), and a couple of other options.
A complete mask set of .13u is close to $1M US. .18u is about half that, .25 about half that again.
It depends on how many layers are required to route all the wires for your chip. Some of the masks in the set are much more expensive, others are cheaper. For many changes, you can get away with only changing one mask out of the 20 and it will only cost about 10k-50k in .18 depending on which mask, other, more extensive changes require you to change several masks, or the whole set if you're completely unlucky.
There are low cost options known as shuttles(
http://www.tsmc.com.tw/download/enliterature/cybershuttle_bro_2002.pdf). Essentially, the FAB runs a shuttle every so often sells off part of the mask to different customers to share the cost. This will cost anywhere between 10k and 50k for the entire mask set, but you are tied to the shuttle schedule and only get your share of the die, plus there's a lot of wasted die on the shuttle because they have to carve it up differently. I think you can expect to get 50-100 die out of a shuttle run. You can use this to work the kinks out of your design, and get the jump on the latest process. TSMC, for example, offers .09u shuttles now.
A wafer costs about $2k US, but that varies quite a bit depending on who you are, how full the fabs are, and whether or not you brought the fab rep to a good enough nudie bar. The cost doesn't vary too much with process(otherwise there wouldn't be much cost benefit from going smaller).
Some fabs will offer free masks to switch to their fabs in attempt to get business, but those offers dry up when the fabs are full (like now).
Finally, if you want to go really cheap, you can prototype on FPGA. You won't get the speed, but you can verify the logic design (though not the timing). Even FPGAs can be pretty damn expensive for an individual hobbyist.
Then you have to package it and test it, the cost of which can be anywhere between 10-50% of the total cost of the chip. (Note: I said "test", which is something you must do for each chip, not "verify" which is what you do to the design to make sure it is correct)
VLSI ASIC design is not something an individual does as a hobby, or even small companies can do without seed money.
