Stupid (?) foundry production questions.

[nelg]

Foundry production questions.

1. Once a chip is in production, what can be done to improve yields? Note, I am asking this based on the assumption that there is no change in masks.

2. On any given process how consistent are things like gate length? For example if a design called for .65nm what margin would be realistic. Looking at this picture

could this be a cherry picked transistor or would it be reasonable to say that the gate length would vary from .5nm to .4nm or not at all?

3.How long do masks last?

4. Looking at this quote...

TSMC and UMC's 0.15u/0.11u lines were envisioned, developed, and marketed as 'cost-reduced' production lines. To achieve this goal, they limit the level of miniaturization to the metal-layers only, allowing the half-node processes to re-use the foundry's investment in already existing/deployed processing-equipment. I'm sure "true" half-node (0.15u, 0.11u) production lines exist elsewhere in the semiconductor industry (like the dedicated DRAM foundries.)

How do you get a reduction in size if you only reduce the metal layers? Please excuse this question if it is overly ignorant.

5. When or will the half step disappear?

 

[rwolf]

You could use a better quality wafer.

 

[RussSchultz]

1. quality control. If the customer can prove the wafer was incorrectly made, the fab will credit them. Also adjusting the process can speed up/slow down things which might be required to make timing.

2. dunno.

3. the reticles last "forever", I think. As far as I know, they don't go bad through use.

4. If you can reduce the size of the routing wires, you can use less layers (cost reduce) or get better performance by having your critical wires have a better path to their destinations.

5. Doubtful.

 

[MuFu]

They are pretty good questions nelg. Definitely not stupid!

So why R430 is smaller than R480? Do the metal changes allow a greater degree of routing/layout optimisation on on the silicon layer (whilst maintaining the same feature size as 0.13u)?

 

[nelg]

1. quality control. If the customer can prove the wafer was incorrectly made, the fab will credit them. Also adjusting the process can speed up/slow down things which might be required to make timing.

What kind of adjustments can be made, also are you referring to production or signal timing?

They are pretty good questions nelg. Definitely not stupid!

 

[RussSchultz]

I don't know the ins and out of it, but through process steps, you can make the transistors "faster" or "slower". I presume there's tradeoff (like higher leakage, but faster transitioning times), but it might just be making it with less blurring or something like that. The steps are things like changing the baking temperatures, or the doping, or other arcane items like that.

Asicnewbie (who, no doubt after all the time he's been asicnewbie, isn't anymore) could probably tell you more about it.

 

[nelg]

Interesting, thanks Russ.

 

[{Sniping}Waste]

Masks should last for many years and very seldom wares out. The masks are made out of Quartz and the image is E-beamed on the quartz. It the mask is cleaned alot then it can ware out. This info is from about 2 years ago and masks could be made with others things but I have not heard of it.

Yield is affected by many things. The big killer is contamanation. Temp, vacuam, timming, and the meteral can change yield.

Half step will likly never go away. Its just a opitic shrink.