Neat project. They are trying to fuse together Multi-threading and Data-streaming in a single architechture. They mapped the Stanford Imagine Stream Processor and Hydra to it with decent results. The link below is from when they used a Mips64 core, and I haven't seen any papers with benchmarks with Tensilca being used. The switch to Tensilica is relativley recent in terms of the projects life span.
http://mos.stanford.edu/papers/km_isca_00.pdf
http://www-vlsi.stanford.edu/smart_memories/
The slides they have are worth a look. Here are a few.
http://www-vlsi.stanford.edu/smart_memories/stuff/posters/SM HW Poster 03-09.pdf
http://www-vlsi.stanford.edu/smart_memories/stuff/posters/SM SW Poster 03-09.pdf
http://www-vlsi.stanford.edu/smart_memories/stuff/posters/SM HW Poster 04-03.pdf
http://mos.stanford.edu/papers/km_isca_00.pdf
The Stanford Smart Memories Project is a research effort to design a single-chip computing element which provides configurable hardware support for diverse computing models and maps efficiently to future wire-limited VLSI technologies. The project involves researchers in VLSI circuits, computer architecture, compilers, operating systems, computer graphics, and computer networking.
http://www-vlsi.stanford.edu/smart_memories/
The slides they have are worth a look. Here are a few.
http://www-vlsi.stanford.edu/smart_memories/stuff/posters/SM HW Poster 03-09.pdf
http://www-vlsi.stanford.edu/smart_memories/stuff/posters/SM SW Poster 03-09.pdf
http://www-vlsi.stanford.edu/smart_memories/stuff/posters/SM HW Poster 04-03.pdf