There's lots of other interesting things as well. Transistor count is in no way inversely proportional to MHz - just because something is ram-packed full of transistors doesn't necessarily mean it's going to run slower.
In fact, the reverse is often true, or so it transpired during my very brief stint as a 3D hardware engineer. Some types of cell may use more transistors and/or silicon area to operate at higher frequencies, for reasons of stability, noise reduction, capacitance, inductance, phase of the moon, etc. etc... It's all a bit of a black art.
The most important thing is to target the design from day one at the right clock speed for the process you're using, the chip cost, and the target market. If you simulate at 300MHz, pay the extra silicon area for more complex noise insulation and routing, and you have good design people, you will get 300+MHz out and with further process optimisation you may push it up evem further. If you simulate at 200MHz, then you're not likely to achieve 300MHz.
I would suspect that is what happened with Parhelia - at the time when they started the project they made a decision to simulate at one particular speed givem the target market - then the market overtook it somewhat.