So, 1 PE after-all or is this just for GDC 2005 ?

[function]

You're absolutely correct, I was thinking of the developer comments I'd read here. I can't actually recall reading the IBM PR quoted. I find it odd that given the reasoned points that respected developers on this board have made, someone would think I was creatively interpreting vauge PR statements from the past when talking about Xenon's processor design.

And of course I could be wrong, its not like I know exactly how MS and IBM built this thing...

I think I regret saying clean sheet, its been quoted to many times...

What I know of its origins is that its not an existing processor design you can buy or read any public information on, that MS asked and got some specific hard to make features (that IBM had problems with) and its quite powerful.

All I ever thought you meant was what they (MS and/or IBM) started without prior constraints and tried to make the best CPU for Xenon that they could. Where existing technology can fit the bill you'd be mad not to use it. Where it doesn't, you engineer somethig new (as your comments above appear to indicate).

Clean sheet: an absence of existing restraints or commitments. No need for everything implemented to be original.

[edit]Sorry for adding to the debate on semantics.[/edit]

 

[Entropy]

Now if you not concerned with FLOPs counts, the PU are clearly very interesting. They are controlling waht the APU are doing, we know they are 64 bit PowerPC cores but have little other (public) information

So lets pose some questions and my views, feel free to disagree. Hopefully this will steer discussion towards meaningful disagreements rather than semantics.

Given the APUs are fairly small (we assume this from the amount of them and there uses), are they PowerPC? More precisely is there any advantage to making APUlet uses the PowerPC ISA?

I'll start the bidding with a no, they are designed as vector processor as such they will likely have a custom ISA for this job.

This would seem almost a certainty.

Are there any advantages to have the PU use a new PowerPC core?
Will they operate any worse as APU scedulers if they used (for example) a PPC970 core.
I'll offer a no, the scheduling will likely want a fairly normal core with good branching. It however may favor a multi-thread core, so prehaps this would be a good change from existing designs.

I would hypothesize that the PU is likely to be rather lightweight in terms of OOO execution capabilities, that is, I doubt it will be as complex as the 970. It will need some extra logic anyway to fulfill its role efficiently, so cutting down on its other complexity would seem to make sense to save die area for the APUs where the heavy lifting will take place.

Where is 'standard' game code going to run?

Given the speciality of the APUs and the fact that game code is often highly unoptimised, I will suggest on the PU. This again suggests prehaps multi-threading (prehaps one thread scheduler, one game code) but with again a fairly standard execution engine.

Agreed. Now, I don't know if it is settled how many PUs the PS3 will eventually have. We've assumed four for a long time.

Do IBM have any PowerPC cores that could with a few modification do the job of a PU

Yes, the PowerPC 300 cores seem to be an ideal fit. Multi-threading, with multi-processing link. High clockspeed, designed for 65nm and simple embedded architecture (no OOOE etc.).

Now I not saying that a PU isn't based (or vice versa...) on PowerPC 300, but the whole arguement that Cell is so revolutionary that everything must be custom doesn't hold if you look at the PU, which to my mind are the 'real' CPUs of the chip. The APUs still look like vector processors doing very specialist jobs, controled by some 'normal' cpus.

Hmm. Don't know much about the 300 series. Do you know where I could read up on it? The 4XX series would also seem to roughly fit the bill.

Now, given the PS3s apparent architecture, what advantages/drawbacks does this have in terms of graphics programming vs the PC paradigm with which most of us are familiar?

Also, is it possible to contrast this with the Xenon CPU?
Without any solid foundation, I've come to get the impression that it is more conventional than the PS3, perhaps descended from Power5 (dual core/dual thread) and with more personal computer type vector coprocessing. What are the most reliable rumours floating around?

 

[DeanoC]

I would hypothesize that the PU is likely to be rather lightweight in terms of OOO execution capabilities, that is, I doubt it will be as complex as the 970. It will need some extra logic anyway to fulfill its role efficiently, so cutting down on its other complexity would seem to make sense to save die area for the APUs where the heavy lifting will take place.

I agree, in general complex OOOE seem to not fit with console systems requirements.

Agreed. Now, I don't know if it is settled how many PUs the PS3 will eventually have. We've assumed four for a long time.

I personally think 1 or 2 PU(s) is more likely.

Hmm. Don't know much about the 300 series. Do you know where I could read up on it? The 4XX series would also seem to roughly fit the bill.

Like all good things 300 series doesn't officially exist ;-)
Some rumours (which sound quite resonable to me...)
http://www.appleinsider.com/news.php?id=323

Now, given the PS3s apparent architecture, what advantages/drawbacks does this have in terms of graphics programming vs the PC paradigm with which most of us are familiar?

Do we assume vertex shading on the GPU or on APUs? Its really the big question with regard PS3, I'll take the assumption the vertex shading is done on the Cell's APUs.
Without the latency hiding hardware that most texture capable shaders have, a texture load will probably expose its latency to the programmer/compiler. Also no fixed function filter would mean a 'texture' load is just an array read.
Interestingly we have example of an architecture today like this... NV40, the vertex texturing support in NV40's VS3.0 requires explict latency hiding, the texture load is pipelined but using the results too early causes a stall. Also it only supports reading of floats without any filtering.

The other big advantage is that of course an APU can loop, create vertices and do complex topology operations quite simply, with its DMA controlled by the APU its would make a very powerful geometry processor just with limited texture capabilities.

 

[Acert93]

DeanoC, thanks for the great posts! A lot of good stuff to chew on there!

 

[pc999]

I must agree with Acert93 lots of good info.

BTW anyone had a idea how Cell would perform in tasks like MRM or procedural synthesis rumored to XeCPU?

 

[Megadrive1988]

hey it would be okay if PS3 had just one PE, but that one PE contained 4 PUs and 32 S|APUs 8)

 

[Alejux]

hey it would be okay if PS3 had just one PE, but that one PE contained 4 PUs and 32 S|APUs 8)

Heh...then I would want a BE , with four PE's totalling 16 PU's and 128 APU's.

 

[SiBoy]

I already expect the ISSCC 2005 presentations will disclose the 1st-gen Cell performance as 256GFlops or less, and people will scream "sub-1TFlops waaaaa!!!!1111" all over the internet, but until "Broadband Engine" (this name is from the Rambus-Sony-Toshiba (which lacks IBM) agreement in 2003, not from the patents) is disclosed in March, I just cross my fingers.

Good to see you're already preparing yourself mentally I expect Vince will do the same.

 

[Mythos]

Just a general statement- we're getting near to what will be known soon about X2CPU and Cell so some good risk taking on a prediction would be cool as our knowledge of CPU design can be put to good use. DeanoC good roll on the thread!

What I know of its origins is that its not an existing processor design you can buy or read any public information on, that MS asked and got some specific hard to make features (that IBM had problems with) and its quite powerful.

The obvious question is what clean design means for the X2CPU and what is being done for CELL?

Lastly, one other consideration is the extensive work that STI has been put in on the manufactoring Tech. (65NM) to address some of the leakage and heat output for the Cell design and what that means towards X2CPU. Will it be incorporated in X2CPU? Will it not?[/quote]

 

[eastcore]

I must agree with Acert93 lots of good info.

BTW anyone had a idea how Cell would perform in tasks like MRM or procedural synthesis rumored to XeCPU?

Yes - I'd like to see some views on this angle.

What impact or advantages might we see from procedural synthesis. I'm pretty sure we all understand its limitations - but is it possible that the design of the X2 might overcome some of them?

For one, we know that the GPU will have direct read access to the CPU cache - I believe this makes interesting things possible, since the shader units in the GPU will be able to process the prodedural data. We know from the patents that the procedural data will contain data that will be suited for processing by the GPU - like "the direction of the wind" - data that can and will most likely be manipulated by the GPU - thus, we are not talking about static models - this is a simple example or indication of way may be possible.

Plus, I've come accross some bull crap rumor from a contact at MS concerning Shenmue 3 and an engine with a strong basis on procedural synthesis. Might the PS3 design be limited in this function, or might developing a game with a stong basis in this procedure become daunghting on the PS3? I say bull crap because Shenmue being developed on X2 is a little unlikely at this point, I just don't see it happening.

What about the limitations on procedural textures + shader units? Do you think the X2 CPU model will excel at procedural textures?

 

[Fafalada]

Given the speciality of the APUs and the fact that game code is often highly unoptimised, I will suggest on the PU. This again suggests prehaps multi-threading (prehaps one thread scheduler, one game code) but with again a fairly standard execution engine.

Your "clean sheet" comments make me want to go on a tangent here

- What do we know of a PU so far?
It's PPC ISA compatible, it would benefit from multithreading hw, likely doesn't need complex OOE like the desktops, and apparently clocks very high (4ghz+), thus implying a new design.

- What do we know of Xenon cores?
They're PPC ISA compatible, they are 2-way multihreaded, they likely don't have complex OOE like the desktops, apparently they clock very high (3.5ghz+), and have been said to be a new design.

Let the readers speculate from here on...

Without the latency hiding hardware that most texture capable shaders have, a texture load will probably expose its latency to the programmer/compiler. Also no fixed function filter would mean a 'texture' load is just an array read.

What if the texture fetch command is exposed on the GPU?
While I don't know NVidia's take on these things, it'd be hard to deny the growing importance of two-way GPU communication.
There's been a fair amount of indication Xenon can do fancy things there , PSP shows that Sony is aware of importance of this as well, and we've seen a lot of ring-bus references in Cell related patents too...
This only in reference to possibility of filtered texture loads mind you latency stuff remains of course, like any other nonsequential DMA fetch, it remains to be seen how we can work around/with them.

Personally I'm also quite interested in alternative datastructure representations for some of the things that can be done with texture fetch today.

 

[Dave Baumann]

- What do we know of a PU so far?
It's PPC ISA compatible, it would benefit from multithreading hw, likely doesn't need complex OOE like the desktops, and apparently clocks very high (4ghz+), thus implying a new design.

- What do we know of Xenon cores?
They're PPC ISA compatible, they are 2-way multihreaded, they likely don't have complex OOE like the desktops, apparently they clock very high (3.5ghz+), and have been said to be a new design.

Let the readers speculate from here on...

Sacrilege!! You heretic you!!!

 

[AzBat]

- What do we know of a PU so far?
It's PPC ISA compatible, it would benefit from multithreading hw, likely doesn't need complex OOE like the desktops, and apparently clocks very high (4ghz+), thus implying a new design.

- What do we know of Xenon cores?
They're PPC ISA compatible, they are 2-way multihreaded, they likely don't have complex OOE like the desktops, apparently they clock very high (3.5ghz+), and have been said to be a new design.

Let the readers speculate from here on...

Sacrilege!! You heretic you!!!

LOL, it's funny how things are coming full circle again, huh? I definitely smiled when I read Dean's PowerPC 300 comment. Personally, I wouldn't be surprised if they were both using the same core, just customized differently. Maybe the PowerPC 300 core is the common link between them?

Tommy McClain

 

[j^aws]

Given the speciality of the APUs and the fact that game code is often highly unoptimised, I will suggest on the PU. This again suggests prehaps multi-threading (prehaps one thread scheduler, one game code) but with again a fairly standard execution engine.

Your "clean sheet" comments make me want to go on a tangent here

- What do we know of a PU so far?
It's PPC ISA compatible, it would benefit from multithreading hw, likely doesn't need complex OOE like the desktops, and apparently clocks very high (4ghz+), thus implying a new design.

- What do we know of Xenon cores?
They're PPC ISA compatible, they are 2-way multihreaded, they likely don't have complex OOE like the desktops, apparently they clock very high (3.5ghz+), and have been said to be a new design.

Let the readers speculate from here on...
...

Meh...old...already done!

...
The PPC 300/350 series look like very good candidates for the Cell PUs and Xenon cores, but this would also suggest Xe CPU at a 65 nm process

http://www.beyond3d.com/forum/viewtopic.php?p=355513#355513

 

[AzBat]

...
The PPC 300/350 series look like very good candidates for the Cell PUs and Xenon cores, but this would also suggest Xe CPU at a 65 nm process

http://www.beyond3d.com/forum/viewtopic.php?p=355513#355513

Brimstone was also reporting that:

It looks like the CPU for the Xbox 2 will be a Power PC 350 variation to me.

http://www.beyond3d.com/forum/viewtopic.php?p=336251#336251

Although the article suggests strongly that the CPU is a Power 5+ derrivitive. I'm unsure about that because of the mysterious Power 350 CPU on IBM's roadmap.

http://www.beyond3d.com/forum/viewtopic.php?p=339843#339843

Although, I believe he was referencing the AppleInsider rumor with that comment he has also provided the following slide on IBM's Power architecure roadmap...

http://www.ibm.com/investor/events/jkelly0504/presentation/slide9.jpg

Nothing there about the PowerPC 300 series though.

Tommy McClain

 

[Megadrive1988]

hey it would be okay if PS3 had just one PE, but that one PE contained 4 PUs and 32 S|APUs 8)

Heh...then I would want a BE , with four PE's totalling 16 PU's and 128 APU's.

why of course 8)

 

[passerby]

So even the Xenon CPU is 64bit? After all dev kits are/were dual-core G5s.

I still think we're missing something with the Cell thingee. Since the first patent was discovered, I've felt that the 'major voodoo' isn't the number cruncing, but the memory/bus design. What we can deduce and reason thus far still does not seem to justify well the amount of $ and effort poured into this thing.

Unless of course, this really IS a disaster. But nah, I hope to be surprised.

 

[Mythos]

-What do we know of a PU so far?
It's PPC ISA compatible, it would benefit from multithreading hw, likely doesn't need complex OOE like the desktops, and apparently clocks very high (4ghz+), thus implying a new design.

- What do we know of Xenon cores?
They're PPC ISA compatible, they are 2-way multihreaded, they likely don't have complex OOE like the desktops, apparently they clock very high (3.5ghz+), and have been said to be a new design.

Let the readers speculate from here on...

However, the devil may be in the details. ISA (Cell) that is...

" However, the ’734 patent refers to “a new architecture for computers, computing devices, and computer networks” and “a new programming model for these computers, computing devices, and computer networks.” Microprocessor Report believes the “new programming model” is a way of binding program code and data together in special bundles, perhaps as part of a new instruction-set architecture (ISA). The ’734 patent describes a much larger register file and other novel architectural features not found in any PowerPC chips today."[/quote]

 

[DeanoC]

I must agree with Acert93 lots of good info.

BTW anyone had a idea how Cell would perform in tasks like MRM or procedural synthesis rumored to XeCPU?

Yes - I'd like to see some views on this angle.

What impact or advantages might we see from procedural synthesis. I'm pretty sure we all understand its limitations - but is it possible that the design of the X2 might overcome some of them?

I think its a dead cert that the PS3 will have some kind of fast link between the CPU and GPU. The hypothesis is simple based on the PS2 (VU1 has a direct link), the rumours about Xenon GPU cache access and common sense (if there isn't a fast link it will be fairly hard to use APUs as vertex shaders...).

I doubt it will be in a form like VU1(where VU1 could set registers in the GS directly), but likely some form of DMA kick to the GPU. There is the obvious problem is synchronisation to be dealt with and I can think of several solution, none ideal. Indeed the more APUs using the GPU the bigger the problem... I suspect the GPU hardware will have support (maybe in the form of multiplexing of command streams?...) for this in some form, it will be important in the PC world soon (multi-core) and has obviously uses in the PS3.

Regardless a Cell APU should be very good a procedural stuff (I'll let Marco talk about MRM, its his 'thing' ). We definately have vector operations and access to reasonable sized tables (something like noise is helped with tables, it would be nice if the table can fit into the onboard RAM but the access is fairly spatially coherent so its not that important).

 

[Pugger]

Although the technicalities of these threads leave me scratching my head, it appears to me, from the coments made in this thread that the XB and PS3 PU are very similar in function if not design. I'm I thinking correct or are they fundementally different.