Revolution out in mid-2006, uses MoSys Ram

[Brimstone]

It's flawed to compare memory bandwidth of GCN to Xbox. It only makes sense if you compare per pin bandwidth if you're comparing specific memory technologies.

I'd assume DDR would still have an advantage.

BTW, bandwidth per pin? But you can up bandwidth by increasing clock speed, which doesn't require increasing pins, I'd think bandwidth per cost would matter more.

Why not combine Rambus differential signaling with the MoSys DRAM design? It would be like XDR but with a better performing DRAM design, although the Mosys DRAM might not clock as high a XDR DRAM, but in return you get the SRAM-like latency.

 

[PC-Engine]

It's flawed to compare memory bandwidth of GCN to Xbox. It only makes sense if you compare per pin bandwidth if you're comparing specific memory technologies.

I'd assume DDR would still have an advantage.

BTW, bandwidth per pin? But you can up bandwidth by increasing clock speed, which doesn't require increasing pins, I'd think bandwidth per cost would matter more.

Why not combine Rambus differential signaling with the MoSys DRAM design? It would be like XDR but with a better performing DRAM design, although the Mosys DRAM might not clock as high a XDR DRAM, but in return you get the SRAM-like latency.

Well then it would be even more expensive...

 

[GwymWeepa]

About the 1tsram on gamecube being 1/3 the bandwidth of the Xbox's, that's because it had less ram. For whatever reason, last gen console's bandwidth was tied to how much they put in, 24 MB main for gc with 2.4 GB/sec bandwidth, ps2 had 32 MB main and 3.2 GB/sec bandwidth, the Xbox had 64 MB of ram and 6.4 GB/sec bandwidth. Clearly there's a reason why each company made sure the ratio was the same.

 

[Megadrive1988]

About the 1tsram on gamecube being 1/3 the bandwidth of the Xbox's, that's because it had less ram. For whatever reason, last gen console's bandwidth was tied to how much they put in, 24 MB main for gc with 2.4 GB/sec bandwidth, ps2 had 32 MB main and 3.2 GB/sec bandwidth, the Xbox had 64 MB of ram and 6.4 GB/sec bandwidth. Clearly there's a reason why each company made sure the ratio was the same.

while I will not say you are absolutely wrong (im not sure), I don't think
this is the case. Gamecube's main memory 1T-SRAM bandwidth is...
2.6 GB/sec, and (AFAIK) this was the result of the downclocking of
Flipper and the entire architecture (except Gekko). when Flipper was
clocked down to 162 MHz, the memory bus & bandwidth also took a hit.
the bandwidth *was* 3.2 GB/sec with the 24 MB of 1T-SRAM before
the downgrade. then when Flipper and buses were downclocked,
the bandwidth was 2.6 GB/sec.

perhaps the numbers for PS2 (32 MB / 3.2 GB) and Xbox
(64 MB / 6.4 GB) are just a coincidence? it doesnt work for
Gamecube though, because it's main memory bandwidth
is 2.6 GB, not 2.4 GB.

 

[Li Mu Bai]

For all that lovely article, it still doesn't explain the performance bonuses of 1T-SRAM. Who cares how it works?! Why should people be excited about it's use? What tangible benefits doesn it actually bring to the console space? Whether it's built of 1 transitor, 6 transistors, carbon nano-tubes of pink elephants is neither here nor there

The Revolution should be utilizing the 1T-SRAM-Q (quad core) technology which achieves four times the density of traditional SRAM's. 1T-SRAM-Q technology, essentially doubles the density of 1T-SRAM memory. 1T-SRAM-Q memory requires a single, non-critical mask addition to industry standard CMOS logic processes adding no more than 5% to the wafer processing cost. (if my source regarding the Revolution is correct)

1T-SRAM-Q memory also includes MoSys' Transparent Error Correction, offering the benefits of eliminating laser repair, improving yield, reliability, and soft error rate while doubling the density. The reduced area of 1T-SRAM-Q memory results in shorter internal signal paths thereby increasing the speed and lowering power consumption.

The benefits of SRAM latency & speed, without the space absorbing transistors on die basically, also without the leakage.

respective random access cycle times:

GDDR3=2ns
MoSys 1T-SRAM-Q (Quad Density)=sub 3ns
XDR DRAM=I could only locate clock speeds of 3.2ghz, anyone know the random access cycle times?

 

[Li Mu Bai]

Factor 5 actually consulted on all next-gen consoles, but for those who have never heard of MoSys outside of the GC, here you are:

MoSys Inc. and Fujitsu Limited Extend 1T-SRAM Technology Agreement to 90nm ASIC/SoC Designs; Targets Portable Consumer Applications including Digital Cameras and Video Camcorders

SUNNYVALE, Calif.--(BUSINESS WIRE)--April 25, 2005--MoSys, Inc. (Nasdaq:MOSY), the industry's leading provider of high-density system-on-chip (SoC) embedded memory solutions announced today the extension of the existing partnership with Fujitsu Limited to incorporate MoSys' 1T-SRAM(R) technology into high volume semiconductor devices for portable consumer applications manufactured on Fujitsu's 90nm process generation.

"We are very impressed with MoSys' embedded memory IP," said Kimiaki Satoh, general manager of the FCRAM Division at Fujitsu Limited. "We now look to offer the same robust memory capabilities on Fujitsu's most advanced 90nm process, following our 130nm process. By offering both 1T-SRAM embedded macros design and wafer foundry services, we will provide our customers with first class ASIC capabilities and the highest quality in the industry."

"We are pleased to strengthen our relationship with Fujitsu and are proud to be their high-density embedded memory technology supplier of choice at 90nm," said Karen Lamar, vice president of Sales and Marketing at MoSys, Inc. "By combining our unique memory architecture and advanced 1T-Q(R) bit cell with Fujitsu's advanced 90nm logic process, designers of complex ASIC/SoC devices will have access to optimal combination of high density, low power dissipating and high performing solutions for their embedded memory needs."

"The contribution of MoSys' 1T-SRAM 130nm at Fujitsu was key for this new joint program targeting 90nm," added Gerry Shimauchi, MoSys International's Japan Country Manager. "By having 1T-SRAM capabilities available at their two most advanced process generations, Fujitsu offers a smooth migration path to their customer's ever more complex system requirements. We look forward to a successful and long-term relationship with Fujitsu."

NEC Electronics Embeds MoSys' 1T-SRAM Memory Technology in 90nm Custom ASIC; Companies Extend Agreement To Use 1T-SRAM In Upcoming Consumer Applications

SUNNYVALE, Calif.--(BUSINESS WIRE)--March 24, 2005--MoSys, Inc. (Nasdaq:MOSY), the industry's leading provider of high-density system-on-chip (SoC) embedded memory solutions announced today the renewal of the existing partnership with NEC Electronics to incorporate MoSys' 1T-SRAM(R) technologies into high volume semiconductor devices for consumer applications manufactured on NEC Electronics' 90nm process generation.

"Since the commencement of our original licensing agreement in March 1999, NEC Electronics has successfully deployed MoSys' 1T-SRAM because of its unique combination of performance, density and power capabilities not available from any other competing memory technologies," said Tom Nukiyama, senior technical director at NEC Electronics America. "We now look to extend our relationship with MoSys to jointly offer our ASIC customers requiring large quantities of high-performance embedded memory a compelling solution to enhance their consumer electronics SoC designs. The manufacturability of 1T-SRAM memory makes it the ideal technology for reducing costs and increasing quality, which is why, at the end of the day, we see it as the ultimate drop-in memory solution."

"We are pleased that NEC Electronics will continue to use our 1T-SRAM embedded memory technologies on even more aggressive processes," said Karen Lamar, vice president of Sales and Marketing at MoSys, Inc. "This combination of our unique memory architecture and NEC Electronics' most advanced semiconductor fabrication technology provides SoC designers with tremendous capability for their next generation of highly-integrated products."

MoSys 1T-SRAM IP Ships in HUDSON Soft's Video Game Controller; Video Game Controller in Volume Production Targets Toy Markets

SUNNYVALE, Calif. & SAPPORO, Japan--(BUSINESS WIRE)--March 14, 2005--MoSys, Inc. (Nasdaq:MOSY), the industry's leading provider of high density SoC embedded memory solutions today announced that HUDSON Soft Co., Ltd. (OSAKA:4822) a leading manufacturer of game software and entertainment equipment, successfully verified MoSys' 1T-SRAM(R) embedded memory technology using UMC's 150nm process technology. The Hudson Soft Video Game Controller is now in volume production using 1T-SRAM(R) technology for its embedded memory.

"1T-SRAM(R) technology made it possible to develop our 32-bit, single chip LSI with network function achieving the required high performance, top quality and cost effectiveness. It had started production and is adopted into electronic toys that have been launched in Japan in November 2004," said Satoru Murakami, Corporate Executive Officer, Head of the Core Technology Division, Hudson Soft.

"We are pleased that Hudson Soft has successfully started volume production," expressed Karen Lamar, MoSys' Vice President of Sales and Marketing. "This comes as a result of the close relationship between Hudson Soft and MoSys teams."

Ken Liou, Director - IP Development and Design Support division at UMC, said, "UMC's SoC solution foundry approach involves working closely with our customers and supply chain partners to achieve production success in the shortest time possible. This effort has paid off again with the successful volume production of Hudson Soft's Video Game Controller incorporating Mosys's 1T-SRAM(R) technology. We look forward to working with both companies for their future product lines."

"The success of this device opens the electronic toy markets for MoSys' 1T-SRAM(R) technology," added Gerry Shimauchi, MoSys International's Japan General Manager. "It proves the advantages brought by 1T-SRAM(R) based products are not limited to communication and consumer applications. Our close relationship with Hudson Soft will allow the development of innovative products for many other application fields."

 

[aaronspink]

respective random access cycle times:

GDDR3=2ns
MoSys 1T-SRAM-Q (Quad Density)=sub 3ns
XDR DRAM=I could only locate clock speeds of 3.2ghz, anyone know the random access cycle times?

GDDR3 and SDRAM technologies in general has random access times in the range of 40-60 nS. 2nS is the data interface cycle time for GDDR3.

 

[PC-Engine]

R520 is said to have 300 to 350 million transistors, which is more transistors than Cell prototype (234 million) or the newer revised Cell (250 million)

they're all supposedly on 90 nm (Cell ver1, Cell ver2, R520) so unless i am missing something here, naturally R520 would be a bigger chip than either Cell.

A large portion of the transistors on CELL is cache...

 

[Fox5]

R520 is said to have 300 to 350 million transistors, which is more transistors than Cell prototype (234 million) or the newer revised Cell (250 million)

they're all supposedly on 90 nm (Cell ver1, Cell ver2, R520) so unless i am missing something here, naturally R520 would be a bigger chip than either Cell.

A large portion of the transistors on CELL is cache...

I thought Cell had almost no cache and it was mostly logic?

 

[PC-Engine]

There is a good amount of cache and LS in CELL.

 

[GwymWeepa]

Alright since Nintendo is going for proven tech, what are the chances that they'll stick a huge amount of the stuff into revolution? Or is 512 megs what's expected?

 

[Li Mu Bai]

Alright since Nintendo is going for proven tech, what are the chances that they'll stick a huge amount of the stuff into revolution? Or is 512 megs what's expected?

It's proven GW, though far from what I would label a "cheap alternative." Still far cheaper than 6-TSRAM, 512mb is what should be expcted, more e-DRAM than the 360 possesses rest assured. I believe that NEC was very influential with Nintendo regarding its adoption, colloborating on the Rev's system LSI & all. Nintendo knows that NEC is quite knowledgeable in its technical choices, any wonder why they're embedding for the 360 as well?

 

[Teasy]

I don't think we can be certain yet that Revolutions main ram will be 1T-SRam, right now we just know it will be used for the embedded GPU memory.

 

[ban25]

The benefits (as I understand them) are 1.) Much lower transistor usage, which equals cheaper manufacturing, and 2.) predictably low latency, which means that code will run faster with less work.

The major drawbacks appears to be lower bandwidth compared to DDR equivalents, and probably higher initial technology licensing fees.

That's lower transistor count relative to SRAM. As for the latency, it's less of an issue for graphics utilization.

 

[j^aws]

...
respective random access cycle times:

GDDR3=2ns
MoSys 1T-SRAM-Q (Quad Density)=sub 3ns
XDR DRAM=I could only locate clock speeds of 3.2ghz, anyone know the random access cycle times?