Real CPU/GPU production cost

[LarsJurgen]

This is a very interesting topic to me. There was a good discussion on the topic a while ago (linked below) but much has happened with new techs & I don't think it fits entierly in the old so I see no reason to revive it.

From what I can gather, once mature, the cost increase to move to a lower tech is very roughly up to 20% extra.

References from AMD & Intel often list taking R&D for fab & chip costs, writeoffs, construction etc into account & land much higher than same tech price from IE TSMC & other foundries. Where their listed price as I gather, is basically the cost for having the wafers run through the fab, without mask. Packaging, error checking included in wafer price generally?

Seen several price references for >$3K for 90 nm & $3k-$3,6K for 65 nm. But these are medium to semi-high quantities. AMD & Intel own their own fab, for two reasons. Tweak the fab to their exact needs & lower price/higher margins, surely they must be getting far better prices on their wafers when done than if they went to another foundry. But how much better?

My interest mainly lies in mature tech, ie not test & new tech's as 45nm for amd when it goes online, although that is interesting also.

http://www.tgdaily.com/content/view/36795/118/
One of a few covering idf giving a reference of roughly $10k per 45nm Atom wafer, which seems very high?

http://forum.beyond3d.com/showthread.php?t=41816
References for GPU die & packaging cost. Some interesting comments.

"I sit in a TSMC info session basically meant to push people to upgrade from 90nm to 65nm."
"According to them, the speed increment is about 15% in general and costs about 15% more."
"The wafer cost is about 3k (after volume discount and technology development agreement, etc)."

http://www.ocforums.com/showthread.php?t=550542
Great thread by JCLW. Only listing
5,3K for 65nm AMD wafer? Seems high?
$4900 Intel wafer, no separation 45/65nm, way out of line with 10K. Yield even higher? IE cache security, X3 etc?

"Assuming:
0.002 Defects per mm^2
$4900 per 300mm CMOS Wafer
$5300 per 300mm SOI Wafer
$2700 per 200mm SOI Wafer
alpha of 1
Dies Per Wafer = {[pi * (Wafer Diameter/2) ^ 2] / Die Area} - {[pi * Wafer Diameter] / (2 * Die Area) ^ 1/2}
Yield = (1 + [Defects per Area * Die Area / alpha]) ^ (-alpha)
$10 burning, binning and packaging cost for single die chips
$15 burning, binning and packaging cost for dual die chips"



CPU/GPU yield, wafer costs on different tech, industry trend (ie price increases for every shrink, seen both TSMC, TI & others mention 1,15-1,2x) & any thoughts on real costs for CPU dies, packaging etc would be of interest. JCLW's post is the only one I have seen on for burning, binning & packaging, especially on multi die chips. How far from target is he? 55nm for AMD & their gpu's? Just how a big edge do they currently hold pricewise?

 

[aaronspink]

CPU/GPU yield, wafer costs on different tech, industry trend (ie price increases for every shrink, seen both TSMC, TI & others mention 1,15-1,2x) & any thoughts on real costs for CPU dies, packaging etc would be of interest. JCLW's post is the only one I have seen on for burning, binning & packaging, especially on multi die chips. How far from target is he? 55nm for AMD & their gpu's? Just how a big edge do they currently hold pricewise?

The problem with this line of questioning is that those who really know, really really can't talk, and those that talk really really don't know. Actual wafer costs and yields at places like AMD, Intel, IBM, etc are highly restricted internal trade secrets for a variety of reasons.

The thing to realize though is that actual silicon wafers don't cost that much and almost all the money is in the cost of the machines inside the building. Compared to the machine loadout, the buildings themselves don't cost that much.

As you get closer to the bleeding edge, the cost of actual new equipment goes up extremely vast, both because of supply and demand (vendors are ramping the tools themselves at the same time you want them), some tools are just inherently expensive due to the high cost of precision, etc. Some tools can last multiple process generations, for example min pitch litho machines have stayed pretty much the same for the past couple generations, with most of the cost going to upgrade/replace the higher pitch litho machines used for the higher metals layers with better ones (you don't need the latest greatest machines to do wide pitch top metal layers, etc).

So as you get to older processes in older fabs you get lower prices primarily because you've already paid off the front loaded debt from the equipment and you are just paying for workers, chem, plant, wafers, and tax.

Its probably possible to get end user wafer costs for someone like TSMC but I doubt you will see AMD/Intel/Etc actually product that information and the people that know can't talk. Even within AMD/Intel/Etc, that information is really on a need to know basis. So the only way someone can publish is to use a lot of educated guesses or get someone to violate their confidentiality agreements.

Aaron Spink
speaking for myself inc.