Gubbi said:
Cycle time is just wrong. 40ns equates to a 25MHz cycle. And cycle times higher than latency
Cheers
Gubbi
You don't understand how DRAM works...
40nS cycle time is very aggresive. most likely they are using 50ns or 60ns cycle time parts.
Cycle time generally refers to random access requiring a full pre-ras-cas cycle for each access while latency generally refers to either having the bank closed and clean requiring only a ras-cas or the page open requiring only a cas.