R520 and G70 32 pipes ?, G70 dual core with turbo cache ?

[Love_In_Rio]

That is what claims VR-Zone in this new http://www.vr-zone.com/?i=2010&s=1
If G70 is dual core, does this mean that its technology would be a small variant of NV40 or, on the other hand, it would imply to be a totally new architechture used also in the PS3 ?

 

[tEd]

It seems they claim a lot lately

 

[Mintmaster]

If the G70 really was just two NV40's, it seems to reflect a trend of what these companies do when they make an advanced architecture. Just double it up, and focus on the next generation after the double up.

NV10 -> NV15
R300 -> R420
NV40 -> G70?

You could sort of say the same for R100 -> R200, but the parallels are much less obvious unless you've had a peek inside. This is not to say that the base architectures are guaranteed to be outstanding hits that slaughter their counterparts, but they have the functionality to carry it over, without radical change, to the next generation.

 

[digitalwanderer]

<FANBOY MODE ON>

It's because nVidia couldn't compete with ATi with only a single chip design...

<FANBOY MODE OFF>

 

[Tim Murray]

NV10 -> NV15

Uttar needs to show up and explain how that's not really the case. NV10 had one TMU and NV15 had two, sure, but NV10's TMU was a trilinear TMU whereas NV15's were bilinear. "Doubling up" isn't really the case here.

 

[Geo]

It seems they claim a lot lately

Yeah, talk about a clear-cut scenario where they are either going to make their names as prognosticators or never be taken seriously again (to the degree anyone does now).

 

[neliz]

Maybe they could team up with L'inq; Inqzone.net

 

[Mintmaster]

NV10 -> NV15

Uttar needs to show up and explain how that's not really the case. NV10 had one TMU and NV15 had two, sure, but NV10's TMU was a trilinear TMU whereas NV15's were bilinear. "Doubling up" isn't really the case here.

I know, you're right. Though, the die size did become quite a bit larger, if I remember correctly, and the base architecture was just about identical.

I just included it to bolster my argument, even though it's only a half truth.

 

[KimB]

As I stated previously, 32 pipelines is highly unlikely this generation. It would require somewhere in the region of 400-450 million transistors. I don't think process technologies are that far along yet.

24 pipelines, as people have been saying all along, is much more likely.

 

[MPI]

People really needs to stop using buzzwords when inappropriate.

"Dual Core"... <groan>

 

[Arun]

GeForce 256: 23M transistors
GeForce2 GTS: 25M transistors
IIRC, the GeForce 256's TMUs weren't working as expected, so they had to be "coupled" (in the drivers, I assume?) to function properly. The indirect advantage of that was "free" trilinear filtering, and the competition wasn't that bad at the time, so they just released anyway. The GeForce2 GTS' doubled bilinear output was just a bugfix. At least that's what I know of it, this information is old and could very well be inaccurate.

As for double core, I would tend to assume they're just interpreting "separate VS and PS chips" in a most original way. Once again, I doubt such a thing is to be seen in the G70, but I don't see it as completely out of the question personally (as I said in another thread, NVIDIA had originally planned to do the same for the NV30! Two lighter chips on 0.15u like that definitively might have worked better than a 125M beast on 0.13u, too)
However, that would be more along the lines of "dualchip", so perhaps they're thinking of something else. Perhaps that VS/PS isn't unified? But then again, all short-term past and future GPUs would be dual-core, except the R500. Another, even more likely explanation, is that they're just clueless jerks.

Uttar

 

[Ailuros]

Well it's not always easy to keep up with the technological advancements, especially for a layman like me. First I had to get used that pipelines no longer exist in the sense they were used in the past and just about when I'm getting used to quads (or SIMD channels) if you prefer, there seems to be some sort of diversion in upcoming architectures, where claiming that it has X amount of quads is no longer absolutely correct either.

As that wouldn't be good enough, some IHVs counted recently TMUs as "pipelines", and now we also get non-unified and unified shader units on top of all that.

An alternative would be to concentrate on fill-rates (like clock frequency * amount of TMUs) and call it a day. In that sense I personally expect from single board configs to not exceed the 10-11 GPixels/sec (bilinear) mark for the upcoming batch and by the end of this year another marginal increase in fill-rate.

 

[Ailuros]

However, that would be more along the lines of "dualchip", so perhaps they're thinking of something else. Perhaps that VS/PS isn't unified? But then again, all short-term past and future GPUs would be dual-core, except the R500.

OT actually and the thought isn't actually mine: what would you call a hypothetical design with separate PS/VS units, but would share ALUs between them? "unified dualchip"?

 

[nAo]

How you would split in 2 a modern GPU?
A chip devoted to rasterizinng and pixel shading and another one to everything else? (vertex shading, primitives assembly, ROPs, ramdac, etc..)
Pixel shading area should take at least half die of current GPU, IIRC.
Obviously it would be needed a very fast (and power area/hungry) interconnection interface

 

[Arun]

How you would split in 2 a modern GPU?

I would imagine the VS and an optional PPP to be in the first chip, and the rasterizer and PS to be on the second chip. Perhaps Triangle Setup would be on the first chip, although I'm not sure what would be best. In such a card, I do agree with you though that the second chip would be bigger than the first, and that would most likely be a major problem with such an architecture. With PPPs being basically out of the roadmap, the problem can only intensify, unless the VS work required increases exponentially, which also feels unlikely. I personally cannot see it happening soon, but who knows.
As for the bus, your best friend tends to be memory, but that's just my personal opinion. 10 million vertices with 8 bytes/vertex would be little more than 80MB

OT actually and the thought isn't actually mine: what would you call a hypothetical design with separate PS/VS units, but would share ALUs between them? "unified dualchip"?

Inefficient POS. If the name had to be more elegant than the design though, I might consider "bidirectional unification of mathematical overhead"

An alternative would be to concentrate on fill-rates (like clock frequency * amount of TMUs) and call it a day.

I disagree; it all depends on the path most of the future games take. Zixels and "high instruction count shaders" performance might be more significative than bilinear performance imo; Xx AF performance and IQ could always have some importance though, I guess. The problem is, simplifying future architectures seems like a a good way to completely misunderstand them, but it also is the only way for the "big public" to understand at least a billionth of them. If anything, the apparent "coolness" of the idea might become more important than the result when it comes to marketing the product.

Uttar

 

[Ailuros]

I disagree; it all depends on the path most of the future games take. Zixels and "high instruction count shaders" performance might be more significative than bilinear performance imo; Xx AF performance and IQ could always have some importance though, I guess. The problem is, simplifying future architectures seems like a a good way to completely misunderstand them, but it also is the only way for the "big public" to understand at least a billionth of them. If anything, the apparent "coolness" of the idea might become more important than the result when it comes to marketing the product.

It's not about strict bilinear performance; in a very oversimplyfied case scenario the average user could IMO easier understand the difference (yes even in relative shader performance) between let's say 8 and 4 GPixels/sec (and yes I would prefer if we'd calculate fill-rate with quad texturing in mind f.e., but the forementioned relativity won't change). Or if I'd have to give the forementioned peak values a name: R420 & NV43.

Do you really think the average user this far has fully understood the real capabilities of the Xenon GPU for instance?

 

[Ailuros]

I would imagine the VS and an optional PPP to be in the first chip, and the rasterizer and PS to be on the second chip.

Unless I've picked up some recent stuff the wrong way, while a Geometry Shader is a requirement for the upcoming API, tesselation units are optional.

With PPPs being basically out of the roadmap....

Part of it only (if the former should be correct).

 

[Megadrive1988]

NV10 -> NV15

Uttar needs to show up and explain how that's not really the case. NV10 had one TMU and NV15 had two, sure, but NV10's TMU was a trilinear TMU whereas NV15's were bilinear. "Doubling up" isn't really the case here.

yeah, and NV15 did not double the amount of pixel pipelines from NV10 - they both had 4.

 

[Skinner]

Well nv did something with the GF6800go, with 12 pipes it keeps almost up with a GF6800U, could be a sign for things to come as far as efficienty is conserned with the G70/80...

 

[KimB]

Well, the really interesting efficiency improvements will be related to the new functionality of FP blending and dynamic branching. Normal rendering performance, while it should factor into any analysis based upon price, just isn't as interesting in my opinion.