Quick Look at AMD/Intel's Financials & Positioning

[B3D News]

Intel and AMD revealed their first-quarter earnings last week and there were also some interesting tidbits in the conference calls. So given the lack of noteworthy news today, let's quickly analyse all of this along with the new CPU rumours that are swirling around the web.

Read the full news item

 

[Time]

Now I honestly don't mean to be rude here but:

(sorry for not covering that properly, I had a pretty long article written but I wasn't happy about it so it got scrapped).

Is that what also happened to the R600 follow up articles .

Also as much as I'd love a consumer priced multi processor system, a.k.a FASN8, I think you forgot about Agena.
Has Montreal (8 cores in one die/package) died?
Couldn't AMD just double the data rate of their DDR controllers - motherboard if socket F/socket F+ isn't designed for 256 bit data transfers?

 

[Arun]

Is that what also happened to the R600 follow up articles .

Hah! I wish...

Also as much as I'd love a consumer priced multi processor system, a.k.a FASN8, I think you forgot about Agena.

Agena/Barcelona? I don't see what I forgot about it? And clearly, IMO, 2P solutions for desktop are gimmicky and will likely remain so. A 1P/6-core solution makes more sense, and unlike 2P or 8-core solutions it might actually sell in decent quantities.

Has Montreal (8 cores in one die/package) died?

That is my interpretation based on current rumours; plus that strategy never made a lot of sense IMO.

Couldn't AMD just double the data rate of their DDR controllers - motherboard if socket F/socket F+ isn't designed for 256 bit data transfers?

Hmm, I don't see how that'd work technically, so I don't think so. Simply using another socket that exposes the memory bus pins from both CPUs seems likely a perfectly fine solution to me.

 

[3dilettante]

AMD can't magically double the data rate of their memory controllers. In servers, they can't expect to support anything more than what JEDEC ratifies.

I believe the new socket G3 is due in 2009, which should fit rather well with the 12-core chips, if they ever come to pass.
I'm not sure if the pin count is officially disclosed, and that socket should come with the MBX memory extender, which is kind of like the memory buffer of an FB-DIMM stuck on the motherboard.
The pin count and altered memory support might allow for a fair amount of wiggle room for increasing bandwidth to the socket.

AMD better have something ready with that socket. Beckton's multiple channels of FB-DIMMs are going to slaughter anything kept at the current memory bus widths, both in bandwidth and capacity.


As for clocking at 45nm, I'd hope AMD could manage to get to the same clocks it got to years ago.
Realworldtech's article on the latest process technologies shows some marginal improvements, if we assume AMD doesn't do much worse than what IBM's shown for 45nm.
The gate oxide is slightly thinner than 65nm, but my Google-fu shows that at 1.2nm, it's only getting back to what it had at 90nm.
Without metal gates and high K gate dielectrics, we can expect something better, but it's not going to touch Intel.
IBM's reticence to show all the numbers for 45nm, particularly for PMOS--which Intel has seriously improved--seems to give the impression we shouldn't hope for too much.

I'm not expecting much of a miracle over 90nm clocks, if that is any sort of a guide.
For the Athlon lineage, it so far has appeared to be the case.
Without a more significant redesign that really adjusts the pipeline to the concerns of finer geometries, the old problems aren't likely to go away.

 

[ShaidarHaran]

Your analysis is sound, however I distinctly disagree with this part:

Furthermore, in the $100-150 market, AMD's positioning is extremely weak as their dual-cores aren't sufficiently fast to capture that market segment while their tri-cores would likely cost too much.

Why would they be unable to sell tris for less money this summer? They're already selling for $165 @ Newegg.

In early 2009, six-core chips from AMD could be very appealing in the desktop market as Intel is unlikely to deliver anything more than 4 cores/8 threads by then. So even if performance per clock was lower, that could still be partially compensated by a higher number of cores.

I can see it now: "huh huh, my 4 core Intel proc is faster than your shitty 6 core amd proc"

So the dual-chip 8-core and 12-core solutions based on Shanghai and Istanbul need to use a 256-bit socket; otherwise they'll be horribly bandwidth limited. We don't know if that's the case, but we certainly hope so.

I'm no E.E., but it's silly to think that any 10h family derivative would ever be starved for system/RAM bandwidth. 10h is a bandwidth monster. Doubling or even tripling cores is unlikely to cause a significant performance bottleneck, or even a perf hit compared to AMD's current 10h parts in memory-bound scenarios or memory benchmarks.

For the Back-to-School cycle timeframe, which mostly affects Q3 but also a bit of Q2, we expect AMD's positioning in desktops to noticeably worsen, while laptops improve. As for servers, we would tend to predict a slight improvement in 1P & 2P but a slight loss in 4P+.

I disagree, on both counts. I predict the opposite to occur.

 

[3dilettante]

I'm no E.E., but it's silly to think that any 10h family derivative would ever be starved for system/RAM bandwidth. 10h is a bandwidth monster. Doubling or even tripling cores is unlikely to cause a significant performance bottleneck, or even a perf hit compared to AMD's current 10h parts in memory-bound scenarios or memory benchmarks.

With a 12-core product, a single socket will have the memory traffic of 3 sockets of Barcelona.
You don't think that might be a little noticeable if the memory situation doesn't change significantly?

Besides, if you're saying 10h isn't bandwidth-starved with 3 times the cores, then you are saying that Barcelona's memory controller was overspecced by a factor of 3.
If there were a way to build a 42-bit memory controller, AMD should have done it.

 

[ShaidarHaran]

With a 12-core product, a single socket will have the memory traffic of 3 sockets of Barcelona.
You don't think that might be a little noticeable if the memory situation doesn't change significantly?

Besides, if you're saying 10h isn't bandwidth-starved with 3 times the cores, then you are saying that Barcelona's memory controller was overspecced by a factor of 3.
If there were a way to build a 42-bit memory controller, AMD should have done it.

Benchmarks don't lie, and if I had access to an AMD system with adjustable HT base clock I'd prove it, but all I have is Intel and all my friends are on Intel or have bargain-basement AMD builds.

 

[Time]

Agena/Barcelona? I don't see what I forgot about it?

But they aren't the same, are they? I thought that their memory controllers, if not other parts of the chips, were optimised for the desktop or server markets. Regardless of that I'm sure Agena has only 1 HyperTransport link while Barcelona has 3 or 4.

And clearly, IMO, 2P solutions for desktop are gimmicky and will likely remain so.

Just for fun I'll shove Core 2 Quad in to the 2P bracket.


About my idea of doubling the data speed from DDR controllers - motherboard, I was thinking along the lines of G3MX.
There would be a chip on the motherboard which the memory controller talks to as though it were 2 channels of RAM at twice the usual speed, that chip then talks to 4 channels of RAM at JEDEC spec. Or a motherboard could link a HyperTransport connection to a second memory controller, the latency wouldn't be as good but AMD is more than used to NUMA.

However having written that I don't see much of a reason to maintain the same socket in the first scenario (other than backwards/forwards compatability) and in the second: a motherboard vendor finishes announcing their plans to increase the memory bandwidth for 1P and 2P AMD systems > everybody applauds and all AMD staff mutter under their breath "duct tape".