Question regarding the cell's PPU

Status
Not open for further replies.

Omeyocan

Newcomer
Hi !

We already know that the cell's PPU is dual threaded, but what do we know about is VMX extension ? 64 bits or 128 bits like Xenon ?

And do someone knows it's theorical performance in terms of GFLOPS ?
 
CELL VMX is "standard" 32 registers (not bits) VMX. The only rumor that was spread some time ago about these unit is that its execution units might have been pimped a bit to allow for better dual threading support.

(remember Cervat Yerli /Crytek stating that PS3s dual threading support is a little better than e.g. a P4 HTs, while 360's is a little worse than that acc. to him; source was a Gamestar.de interview some time ago...)

that's pretty much all i can remember right now of about this topic :)
 
Hi !

We already know that the cell's PPU is dual threaded, but what do we know about is VMX extension ? 64 bits or 128 bits like Xenon ?

And do someone knows it's theorical performance in terms of GFLOPS ?

The Cell is, afaik, completely and utterly described in full on IBM's website. ;) You might like to try looking into the Programmer's Manual ...

http://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/9F820A5FFA3ECE8C8725716A0062585F

EDIT: I think you're looking for what's in chapter 23.
 
Hi !

We already know that the cell's PPU is dual threaded, but what do we know about is VMX extension ? 64 bits or 128 bits like Xenon ?

And do someone knows it's theorical performance in terms of GFLOPS ?


Same as Xenons

(remember Cervat Yerli /Crytek stating that PS3s dual threading support is a little better than e.g. a P4 HTs, while 360's is a little worse than that acc. to him; source was a Gamestar.de interview some time ago...)

that's pretty much all i can remember right now of about this topic

Isn’t a rumour apparently because Cervat wasn't the only one that stated this .
 
Status
Not open for further replies.
Back
Top