It may be a longer road, but there ought to be a shrink possible.I know this is bordering a little on off topic, but will there be any potential die shrinks available for a next-gen console launching at the 7nm process node?
Will this likely impact the design, i.e. perhaps a motivation to future proof by going "bigger" or even going "smaller" depending on whether you think future-proofing performance is more important than future-proofing price?
Perhaps they'll shift towards a design with more emphasis on clock speed to mitigate the inherent cost of a larger chip although I'm not sure what the crossover point is between yields affected by wafer defects vs target clocks TDP.
Scorpio's "Hovis method" sounded like they were speed binning chips and then adjusting voltages to clock the chip appropriately i.e. overclock/underclock, so they are potentially throwing TDP variability into the mix in order to get higher # of usable chips @ target performance. The question there is how much does it cost them for a suitable cooling system and what variance is tolerable, but ultimately their internal projections must have shown that it was worthwhile...
16nmFF certainly isn't cheap at the moment, and before the reveal there was speculation as to how wide they would go in order to hit 6TF in the first place given an expectation of low clock speed (relative to desktop counterparts). With the new info, it seems there are things they have to do in order to balance the chip size & costs there.
¯\_(ツ)_/¯
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