http://www.imgtec.com/News/Release/index.asp?NewsID=601
8 ALUs per core? *faints* I wonder how many TMUs those have.
8 ALUs per core? *faints* I wonder how many TMUs those have.
PowerVR SGX554
- Thread starter Ailuros
- Start date
If the 554 keeps the 2:1 ALU:TMU ratio of SGX cores (535 being the exception here), then it should be 4 TMUs.
They haven't though revealed other critical details like some performance figures and/or die area and it doesn't come as a surprise either since the competition doesn't mention any such details yet either. If each core has 4 TMUs the die area should be over 16mm2@65nm/200MHz, as it'll capture more than a SGX543 2MP due to DX9 L3 compliance. Alone the fact that TMUs for 544 and 554 support 4096*4096 texture sizes should add in a fair amount of additional transistors.
Granted integration for any sort of 554 will take its typical time meaning that 65nm is out of the question and even 45nm could be questionable, but still the die area isn't exactly small either.
However in the grander scheme of things if one takes the maximum latency of the design and considers what kind of beast a 554 16MP@400MHz could create in theory and then sets a parallel with power consumption and/or die area the results should be quite impressive. 128 ALUs, 64 TMUs.
The downside then is who and why would want any such >4MP 554 beast when I look into AMD's Ontario direction for instance.
AMD's Fusion variants are all DX11 from what I can tell; in that regard perf/W (not mW!) and perf/mm2 comparisons for >tablet devices could be questionable exactly because of the higher DX level of the first.
By the way they had a storm of public announcements yesterday and this one isn't short of impressive either:
http://www.imgtec.com/News/Release/index.asp?NewsID=597
They haven't though revealed other critical details like some performance figures and/or die area and it doesn't come as a surprise either since the competition doesn't mention any such details yet either. If each core has 4 TMUs the die area should be over 16mm2@65nm/200MHz, as it'll capture more than a SGX543 2MP due to DX9 L3 compliance. Alone the fact that TMUs for 544 and 554 support 4096*4096 texture sizes should add in a fair amount of additional transistors.
Granted integration for any sort of 554 will take its typical time meaning that 65nm is out of the question and even 45nm could be questionable, but still the die area isn't exactly small either.
However in the grander scheme of things if one takes the maximum latency of the design and considers what kind of beast a 554 16MP@400MHz could create in theory and then sets a parallel with power consumption and/or die area the results should be quite impressive. 128 ALUs, 64 TMUs.
The downside then is who and why would want any such >4MP 554 beast when I look into AMD's Ontario direction for instance.
AMD's Fusion variants are all DX11 from what I can tell; in that regard perf/W (not mW!) and perf/mm2 comparisons for >tablet devices could be questionable exactly because of the higher DX level of the first.
By the way they had a storm of public announcements yesterday and this one isn't short of impressive either:
http://www.imgtec.com/News/Release/index.asp?NewsID=597
It also states the following:
Some food for thought on that one:
http://www.xbitlabs.com/news/multim...ss_on_Game_Console_Market_Game_Publisher.html
Nice offer Rys; unfortunately I'm certain that all questions I would like to ask fall into the category of questions you won't be able to answer
OK, lets see:
The 543MP allows up to 16 GPU's, therefore how does the GPU-system handle the vertex processing. round robin? Processes each GPU one vertex from a batch of 16 or how is it handled?
How high is the vertex bandwidth demand for a SGX-TBDR in general and how high is the bandwidth demand for the vertex handling in a MP configuration (for example 543MP with 4/16 GPUs). I'm sure that different games have different requirements due to buffers, deferred shading, shadows etc.. so maybe you can specify different requirements and give a range of vertex bandwidth per 1Mio vertex.
I hope you can decipher my layman bla bla..
I was wondering what, if any, software was presented on the 543MP set-up. Was it any of the typical demos (in-house shader views, Extreme Ball, etc)? If so, can any performance/framerate details be shared?
I imagine disclosing details about the hardware might have to wait on Renesas, but I'd be interested in, if possible, knowing whether it was a 543MP2 and what the CPU and bus configurations were?
I imagine disclosing details about the hardware might have to wait on Renesas, but I'd be interested in, if possible, knowing whether it was a 543MP2 and what the CPU and bus configurations were?
Significantly lower than the competition
Significantly lower than the competition
ROFL...sorry I couldn't help it but that isn't particularly telling but we know that you folks can't be more precise. That's why I keep myself from asking these type of questions.
mboeller,
http://v3.espacenet.com/publication...b&FT=D&date=20100915&CC=EP&NR=2227781A1&KC=A1
http://v3.espacenet.com/publication...T=D&date=20090604&CC=WO&NR=2009068893A1&KC=A1
Patents of course won't go into any details how the final implementation may be in hw, but it might give you an idea how they handle it.
By the way I think but am not sure that sure that Extreme Ball here: http://www.imgtec.com/demo_room/vie...OWERVR Graphics&DemoDev=Imagination&#ViewPort was rendered on a SGX535.
1M Tris/s is a quite a bit more than the 1M vertices you're asking for I guess
It is likely that the chip being demoed by Renesas was their new SH-Mobile AG5 Soc, which they will be supplying to NEC,Panasonic and sharp amongst others. Very little info about the chip, but timeframe would suggest it is the 543MP chip.
http://www.renesas.com/media/edge_ol/application/02/r70pf0010ej0101_edge.pdf
http://www.renesas.com/media/edge_ol/application/02/r70pf0010ej0101_edge.pdf
Significantly lower than the competition
should I cry or should I laugh?
That's exactly the sort of answer I had expected.
Don't you think that all your competitors have analyzed your GPUs (MBX/SGX) long ago so for them this information is rather boring old. You were/are the leaders in the handheld market (by far) and therefore your competitors will at first look what strength and weaknesses your GPUs have because you are their biggest competitor.
Thanks for the links!
should I cry or should I laugh?
That's exactly the sort of answer I had expected.
Don't you think that all your competitors have analyzed your GPUs (MBX/SGX) long ago so for them this information is rather boring old. You were/are the leaders in the handheld market (by far) and therefore your competitors will at first look what strength and weaknesses your GPUs have because you are their biggest competitor.
We've updated this area of our technology with pretty much every generation so I doubt that our competitors know as much as you think, or at least probably haven't understood all the implications.
We are looking at doing some technical papers/articals that will certainly give a bit more information than is available now and hopefully dispel a few myths, but don't expect us to give out hard figures on things like this!
John.
So I only now realised that the 554MP is a 4xTMU per core design while the ARM T604 is a 1xTMU per core design that only scales up to 4 cores. I'm not certain, but the T604 looks like a 2xVec4 MADD design, which means 16 flops/TMU. Series5XT has two 'pipelines' per TMU, each of which delivers 4 MADD, so that's also 16 flops/TMU. Some performance and area comparisons between the two would certainly be very interesting!
EDIT1: Assuming they're keeping the same ALU:TEX ratio, of course. Hmm!
EDIT2: Gah, yes, I obviously meant 554 not 544 (see thread title!), even thought I fixed that in my previous edit. Bah! And the EDIT1 disclaimer obviously matters.
EDIT1: Assuming they're keeping the same ALU:TEX ratio, of course. Hmm!
EDIT2: Gah, yes, I obviously meant 554 not 544 (see thread title!), even thought I fixed that in my previous edit. Bah! And the EDIT1 disclaimer obviously matters.
