Possible Xbox2 processor configuration?

[bbot]

Someone on another website posted this:


"Someone screwed up the specs in the retelling. It basically is one processor with three processor cores: Two 980 cores, one VMX2 core. Total of three processors. The 980 is a real SMT core unlike the Pentium 4, and will be able to handle up to 5 threads simultaneously en toto. Two per non-vector core and one for the VMX core.

Why is it real? because IBM double the power of each functional unit to handle the additional workload of the multiple threads in addition to doubling memory registers etc."


Does this make more sense than having three separate G5 processors or one or three separate PPC976 processors?

 

[Deadmeat]

...

No it doesn't.

Altivec (aka "VMX2") is not a separate processor core anymore than a FPU, it depends on the host CPU's load/store unit and program counter to do its job. Thus it is never counted as a stand-alone processor, unless you come from SCEI land.

The 980 is a real SMT core unlike the Pentium 4, and will be able to handle up to 5 threads simultaneously en toto.

Power5 does two threads per core, no more. What is being claimed above requires a major redesign and is very unlikely.

 

[Guden Oden]

Except, looking at the schematics of the G5 CPU at Ars Technica for example, shows VMX to not be a separate core. It's actually deeply integrated into the processor, the scheduler, instruction fetch/decode etc. Pulling it out of there not only seems counter-productive, but also a whole lot of work for no apparent reason.

I doubt the quote you posted is correct.

 

[MrWibble]

My reading of the original post was that the chip would contain two HT enabled PPC cores with no VMX, and one single-threaded core *with* VMX.

That gives 3 cores and 5 simultaneous threads. Perhaps some general purpose horsepower coupled with something a little more specialised for driving geometry before it hits the gfx chip? Might actually be a reasonable configuration.

I have no idea of the validity of this claim or otherwise however - just pointing out what I think is meant...

Amazing how you managed to get a dig at SCEI into this thread already DM...

 

[Megadrive1988]

what will be far more important is how many Geometry Engines
(today called Vertex Shaders) ATI puts in Xbox's R500 derivative.

 

[Dave Baumann]

what will be far more important is how many Geometry Engines
(today called Vertex Shaders) ATI puts in Xbox's R500 derivative.

My guess: the same number as they do pixel shaders!!

 

[Deadmeat]

...

My reading of the original post was that the chip would contain two HT enabled PPC cores with no VMX, and one single-threaded core *with* VMX.

Why would IBM stick in two different PowerPC cores on a single chip??? Why do the work twice when you can do it just once??

Of course that original XCPU article was poorly written by some guy who doesn't understand computer architecture, and your poster is coming up with a possible configuration from a faulty info...

 

[Panajev2001a]

Amazing how you managed to get a dig at SCEI into this thread already DM...

That is why I love him

 

[bbot]

The thread about Power5 MCM has made me think: what if they could shrink the chip down from using a 130nm to 65nm process? Could it be possible to place all eight processors core onto one die? What about cost?

Which cost less to produce: a four processor MCM or four separately packaged processors?

 

[Megadrive1988]

many months ago.... maybe more like a year or so, I asked about Power4
MCM. it's pretty similar to a Power5 MCM, that is, *four* duel-core processors in a chip package with all the interconnects and caches.

a modified Power5 MCM might be just what Xbox2 and/or N5 needs.

 

[Fafalada]

My guess: the same number as they do pixel shaders!!

I second that guess

DM, I thought the above rumour was disqualified in DM land by default just because it mentions AltiVec.
After all you've already proven that XBox2 will not have any SIMD enabled cores at all, haven't you? 8)

 

[Deadmeat]

...

what if they could shrink the chip down from using a 130nm to 65nm process? Could it be possible to place all eight processors core onto one die? What about cost?

MS is in a cost-cutting mood; it won't pay extra to gain a few extra performance.

The maximum die size MS will probably swallow is 100 mm2. At this size IBM can fit uptp 4.

 

[DeanoC]

Re: ...

Altivec (aka "VMX2") is not a separate processor core anymore than a FPU, it depends on the host CPU's load/store unit and program counter to do its job. Thus it is never counted as a stand-alone processor, unless you come from SCEI land.

The Xbox 2 CPU will certainly have an Altivec (or something based on it) unit

As for what counts as a seperate core, depends on your defination. Defination I'd use would be if each 'core' is a complete Von Neuman model processor by itself. Which means I'm from SCEI land. How would you define a 'core'?

SSE and Altivec are part of a core, whereas a VU is a core. As each VU has a load/store unit and a program counter. Or have you never played a game running completely (logic, gfx, etc) on VU1? I have.

 

[bbot]

What about my second question? Suppose MS chooses to go with four 65nm process, dual-core processors. Will it be cheaper for MS to go with four separate processor packages or with a single MCM?

 

[Qroach]

IMO it'd be far cheaper to go with a single chip over multiple chips. Just think of how they'd have to connect multiple processors to a mother board and the extra traces and sockets needed to do that would certainly increase the over all cost of a motherboard.

 

[Guden Oden]

I can't believe traces REALLY cost that much money. After all, mobos are basically nothing more but fibreglass laminates with layers of etched copper film at certain depths.

One chip with multiple cores will be bigger than a chip with just one core, all other factors being equal, and will hence have a (perhaps even significantly) lower yield, thus making it more expensive.

This will also have to be factored in...

 

[Qroach]

Making a motherboard that supports multiple chips is expensive, much more expensive then a single chip mother board. There's all sorts of issues related to having multiple chips on a single motherboard. If you recall 3dfx with the voodoo 5000 had to make many changes to accomodate multiple chips

One chip with multiple cores will be bigger than a chip with just one core, all other factors being equal, and will hence have a (perhaps even significantly) lower yield, thus making it more expensive.

or you could have 4 chips with a low yeild, therefore making things more expensive. A single chip with multiple cores will always be less expensive in the long run compared to 4 individual chips. why do you think sony went from multiple chips in the PS1 to a single chip with everything on it? Why? it's more cost effective.

 

[V3]

What about my second question? Suppose MS chooses to go with four 65nm process, dual-core processors. Will it be cheaper for MS to go with four separate processor packages or with a single MCM?

That specific Power5 MCM has like over 2000 mm2 of total area. Even using 65nm process its hard to fit all those chips and those L3 cache onto one chip of reasonable size.

You can redesign those Power5 MCM though, strip the 8 MB L2 cache and 144 MB L3 cache, and just put 512kB-1MB L2 cache and 8 cores and it'll be around 150 mm2 chip on 65nm.

 

[V3]

or you could have 4 chips with a low yeild, therefore making things more expensive. A single chip with multiple cores will always be less expensive in the long run compared to 4 individual chips. why do you think sony went from multiple chips in the PS1 to a single chip with everything on it? Why? it's more cost effective.

Depend on the size of the chip.

 

[Riddlewire]

Didn't Sun announce a technology last year that would enable chip to chip communication through edge contact?
Is that something that would reduce the complexity (and cost) of the motherboard by eliminating some of the traces that usually accompany traditional board-bound interconnects? It's also supposed to dramatically improve performance by essentially making two chips act as one.
Is something like that applicable in a case like this?