PCI-SIG set to draft PCI Express Gen3 by year end

[B3D News]

The PCI Special Interest Group, which controls the PCI Express specification, looks set to draft the 3.0 revision of the interconnect by the end of 2007, for review process and refinement in 2008, with devices and hosts appearing in 2009.

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And, Wheee!, 5,000th thread in 3D Tech!

 

[fellix]

At last - a low latency serial peripheral bus. Let's hope this will do Creative (and the rest) to put more high stakes on PCIe implementations.

 

[silent_guy]

At last - a low latency serial peripheral bus. Let's hope this will do Creative (and the rest) to put more high stakes on PCIe implementations.

Why do you think it will be lower latency than existing PCIe?

The only real technical matter they talk about is the bit/symbol ratio, but that has nothing to do with latency. Depending on the kind of error coding they want to add, I would expect latencies to increase or stay stable instead of decrease.

On the whole, I don't think PCIe latency is as much of a problem as efficient bandwidth usage: there's quite a lot of address related overhead, so you need really large data packets to compensate. But it's not always possible to find enough useful data to transfer.