PCI-Express question

Quitch

Veteran
I'm speccing up a PC for someone and that means its time to learn about hardware again! :) Unfortunately my new job keeps me busy, so I can't spend all day reading Beyond3D and arstechnica anymore.

I note that the various boards out at the moment tend to have a 16x PCI-E slot for the graphics card, then 2 or 4 1x PCI-E slots, along with a few PCI slots. How does 1x PCI-E compare to the old PCI? Will that do for the future, or do we expect to see 2x+ allocated to these slots in future generations?
 
Quitch said:
I'm speccing up a PC for someone and that means its time to learn about hardware again! :) Unfortunately my new job keeps me busy, so I can't spend all day reading Beyond3D and arstechnica anymore.

I note that the various boards out at the moment tend to have a 16x PCI-E slot for the graphics card, then 2 or 4 1x PCI-E slots, along with a few PCI slots. How does 1x PCI-E compare to the old PCI? Will that do for the future, or do we expect to see 2x+ allocated to these slots in future generations?

One PCIe x1 (the x1 signifies a single 'lane') is equivalent to double the bandwidth of PCI@33/32bit (133MB/sec) in one direction. However, PCIe is, by nature, full duplex so you can transmit a total of 512MB/sec per 'lane'. This distinction is the key to how PCIe will help improve system wide data transfer. There is no more jockeying for send/receive state. This is often an overlooked facet of PCIe, with people mostly wanting to read raw MB/sec numbers. Seldom is it mentioned that how the transfers are taking place have changed.

The PCIe x16, or PEG (PCI Express for Graphics), is the most obvious as there is a strong incentive to use this. Although other devices (all) benefit from using PCIe, other players may be less motivated to assume the risk of creating PCIe products when PCI suffices or to incur the wrath of dual assembly lines for what may be perceived as identical products differing only in connector type. It is interesting to note that you reap the greatest benefit from PCIe when the whole system operates on it. The mixed breed we are seeing now must still synchronize with legacy and this may hamper performance.

There are already boards with x4 slots (1 GB/sec) and this width is likely to be popular with those needed bandwidth for I/O intensive add-in boards. The x2 is a bit 'iffy' because this bandwidth is in no-man's-land. PCIe x1 is good because it's cheap and useful for lots of stuff (like audio hardware, Firewire card, etc), but once you have 'real demands' you probably want more than double that. This makes the x4 a better choice.

All the talk of Nvidia's SLI implementation seems to have overshadowed the fact that the dual PCIe x16 that SLI requires (well, really it's x8, I believe) have caused a double jump in the industry from AGP x8. First PCIe x16 and then two of them. Looking at the size of the connector, it's clear that x32 is not looking very viable; it would be nearly twice as long and probably exactly twice as long with the additional power pin-outs that such hardware would demand. So, the question then becomes "what will the next step be?" because there is always a next step. Will the dual PCIe x16 solution prevail or will Intel revise with a PCIe2 ruinning at twice the frequency, or perhaps only double the frequency of the PEG link/lanes? I have no idea and I was actually going to post asking that very question myself. The dual PCIe x16 as a solution seems too clunky. I would bet they just double the frequency of the PEG, leaving the other PCIe lanes as they are for now.

Bah...I forgot the all-important link: PCI Express at Intel

They have two PDFs right there on the front page. The larger one is nice as it is in the form of presentation slides.
 
The pins in the current x16 slot aren't staggered like with AGP. Increasing pin density would not be a major endeavor I'd think, look at how many pins they fit on a DDR2 DIMM... Also, in the x16 interface, very few pins are actually signal pins, so doubling that part of the connector would not mean a doubling of the connector length. Power and ground pins could remain more or less the same.

That's not the way Intel wants to go though I believe, as a signalling speed increase is planned for 2006-ish... I believe the actual speed of the interface will be negotiable between client and host in a couple intermediary steps too... Will be interesting to see what happens.
 
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