P + E Cores ?

[arandomguy]

Good news according to an intel document the new cpu's may stop some games protected with drm from working

Can you provide a link? This sounds really weird. Whilst some threads may benefit from running on certain cores - or combination of cores - and can definitely determine which CPU core(s) they are running on, I can't fathom why a DRM implementation would be written in a way as to cause problems.

Just an update on this since there is post launch information now. There is some discrepancies I've seen with the numbers but there were roughly 90 or so Denuvo games impacted. 20 - 30 have yet to have been fixed although it's still being worked on until launch. There might be 10 - 20 yet to be fixed even post launch. The issue being that while Intel can work with Denuvo to address the DRM side any fix also will be developer/publisher dependent on putting into the games build. Given the amount of games I'm assuming this extends as far back as Denuvo first appearance in 2014 (7 years), so there is going to be some games likely in the dated/no longer supported category.

The issue seems to be due to the two core types being flagged as essentially 2 separate systems which is tripping protections. A theorized workaround, which was floated since the original news, would be manually setting affinity so the game only runs on one type of core or disabling the E cores.

This issue (and the work around) may apply to other DRM that has similar principles other than Denuvo.

Could this hybrid approach cause frame pacing issues in games?

From what I remember in the developer guide it was a possibility. But in theory so could anything that results in a non uniform resource scenario, whether that be SMT or chiplets which we have examples of and have seen issues with particularly at first/early adoption.

How does the DDR4+DDR5 compatibility work in Alder Lake (or past cross-generation CPUs)? Does that mean the CPUs have separate PHYs for each or are they dual purpose? Not sure how that works.

I couldn't find an official Alder Lake thread yet.

I don't know strictly physically per say but in terms of die shots for both Skylake (DDR4 + DDR3L) and Alder Lake the PHY at least physically appears as one bloc, or it's two blocs next to each other.

If you mean from a usability stand point there hasn't been a consumer case in which both can be used simultaneously. Past transitions such as with C2D (DDR3/2) and Skylake did have motherboards that could support both memory types but it was a 2 slots of each type one or the other scenario, you had to pick what was installed at boot up. There are no DDR5/4 hybrid boards announced yet and they were very rare for Skylake.

In any case the actual slots are not physically compatible and have always been physically keyed differently to prevent accidental insertion of the wrong type.

 

[Malo]

If you mean from a usability stand point there hasn't been a consumer case in which both can be used simultaneously. Past transitions such as with C2D (DDR3/2) and Skylake did have motherboards that could support both memory types but it was a 2 slots of each type one or the other scenario, you had to pick what was installed at boot up. There are no DDR5/4 hybrid boards announced yet and they were very rare for Skylake.

Yeah I know they can't be used simultaneously, and any possible dual 4/5 boards will be very rare. Was just curious from a PHY perspective how it's handled in the CPU.

 

[Davros]

but there were roughly 90 or so Denuvo games impacted. 20 - 30 have yet to have been fixed although it's still being worked on until launch. There might be 10 - 20 yet to be fixed even post launch

Wow I never expected the number of affected games to be so large.

 

[hoom]

Is it fair to say that AMD already gets a partial big.LITTLE effect with the multi-chiplet implementations using different binned chiplets with lower boost/voltages?
Being all the same core implementation & not huge clock/voltage differences its limited but also won't have that compatibility issue as all cores will look the same to software other than clock.

Might AMD 'respond' cheaply with a more defined/marketed Performance chiplet + Efficiency chiplet split?

 

[Malo]

Is it fair to say that AMD already gets a partial big.LITTLE effect with the multi-chiplet implementations using different binned chiplets with lower boost/voltages?
Being all the same core implementation & not huge clock/voltage differences its limited but also won't have that compatibility issue as all cores will look the same to software other than clock.

Might AMD 'respond' cheaply with a more defined/marketed Performance chiplet + Efficiency chiplet split?

You might be right there, if it's only about priority. I've wondered whether the efficient cores are only used for certain tasks or if windows will use either for any task simply based on perf demands for threads. Does an application need to be programmed specifically to utilize the E cores or will they be used regardless?

 

[Kaotik]

. Does an application need to be programmed specifically to utilize the E cores or will they be used regardless?

They get used regardless

 

[Davros]

Workaround steps for end-users to enable Legacy Game Compatibility Mode with affected games that have not received a software fix:

Power-up system and enter system BIOS setup.
Enable switch Legacy Game Compatibility Mode to ON (one-time only) in BIOS.
Save BIOS setup changes and exit.
Boot to OS.
Toggle Keyboard Scroll Lock key ON.
Launch affected game title.
Toggle Keyboard Scroll Lock key OFF after ending game title.

 

[hoom]

Almost like a Turbo button again

 

[arandomguy]

Is it fair to say that AMD already gets a partial big.LITTLE effect with the multi-chiplet implementations using different binned chiplets with lower boost/voltages?
Being all the same core implementation & not huge clock/voltage differences its limited but also won't have that compatibility issue as all cores will look the same to software other than clock.

Might AMD 'respond' cheaply with a more defined/marketed Performance chiplet + Efficiency chiplet split?

I mentioned this in an earlier post and I'll go into a bit more detail here. The "efficiency" cores while labeled that way is not strictly referential to power efficiency.

Essentially the philosophy behind the design is that work loads tend to be split into 2 criteria -

1) Time critical and latency sensitive. These work loads tend not scale out wide or distribute evenly across threads.

2) Throughput based workloads. These tend to scale out very wide and evenly in terms of distribution.

But from a design stand point how you would approach tackling 1 vs. 2 is very different. With a hybrid design you can afford more specialization. One core will be bigger and you only need a few of these. The other smaller one can be designed in mind for scalability in terms of core count.

If you look at the ADL die shots for example the big advantage the "E" cores have is you can put in 8 of them for only slightly more than the die space of 2 "P" cores. This makes them much more efficient for tackling workload #2 scenarios from a design cost perspective even without factoring in power efficiency. So essentially a 8P+8E config will provide the same performance as a 10P configuration in workload #1 but more performance in workload #2. Or alternatively it'll provide more workload #1 performance than a hypothetically compromise design for the P cores.

 

[hoom]

Well we know somewhat more about both Intels implementation & what AMD has upcoming since that post.

I will still argue AMD is coming from a situation with more cores available & cheaply via multi-chiplets because they're using an intermediate size core.
They've already been making multi-chiplet processors with 2nd+ chiplets using lower voltage/max clock binned chiplets -> allowing workload 1 to run at max performance on higher clocking/voltage first (preferred) chiplet & workload 2 to run somewhat more efficiently on all chiplets at lower clocks.

My suggestion was they could maybe bin that even more aggressively with a bigger & directly marketed performance difference.
As an eg & not real numbers: a 2-chiplet Processor with a top binned first chiplet having 3.8Ghz base, 4.7Ghz max boost (5800X stats) then a much slower bottom binned 2nd chiplet with say 3.8Ghz max & correspondingly low extra TDP, lets call it R7 5875.
You get the workload 1 performance of a 5800X but extra 8 cores for workload 2 with minimal extra TDP compared to 5950 where the 2nd chiplet has closer to the same performance as the first.
Does mean you need to make a 2-chiplet processor vs 5800X & would depend on yields/the extent of use in other products of those top & bottom binned chiplets (as I understand the bottom bins go into EPYCs so they may not be available)


Anyway, now we know AMD has a cut-down Zen4 variant that they're going to put 16 of on a chiplet for dedicated workload 2 environments & allegedly will mix an 8-core 'P-chiplet' with a 16-core 'E-chiplet' giving a proper big.LITTLE.
But not until quite a way away end of 2023 which seems a bit late IMO.