OMAP 2420 Dev Board and Renesas SHMobile Board

Which chip is this?

 

That's what I'd like to know myself; it's in Samsung's future roadmap (check the recent pdf at Khronos' website).

 

Ailuros: I decided to remove that because it really wasn't topic related and it really didn't give any additional information as off-topic either.


anyways, interesting picture. If I have any clue left from the days I was really interested 3D HW stuff, it looks like capable doing some SM 3 related stuff like vertex texturing... There's TMU / texture engine for vertex unit as well as the "per frag. unit" looks like special unit that has access to main Bus. So, it could be used for some kind of specialized AA perhaps...

 

It's the primitive engine that caught my eye.

 

Could it be MBX 2?

http://www.beyond3d.com/forum/viewtopic.php?t=22093

 

well, it's after vertex shader, so most likely it is just primitive setup.

(High Order Surfaces and Basic Geometry Primitives would need to be tesselated before vertex shader, right? )

So, most likely it is Primitive Processor as same way as Pyramid 3D had one: it just constructs triangles for rasterizer.

 

umh... if it is, I am a bit disapointed. besides, I doubt Samsung would have right to distribute charts about licensed unreleased technology.

 

Most likely yes; if it should be programmable though (which I consider unlikely at this stage) we'd be talking about more rapid advancements in the PDA/mobile than I could have imagined.

In a best case scenario they could have some sort of commitment at this stage, which would make the chances of releasing any specs this early even smaller. AFAIK didn't license MBX Lite directly from IMG either.

The charts aren't that much telling either if you think about it. One of them states PowerVR MBX and the "FIMG" in question (for the future) just states "programmable" and not who'd design that thing. Has Samsung a graphics department or not?

As I said the best you can get out of those graphs is an architecture with programmable PS/VS. What exactly would you expect for the second generation of PDA/mobile chips anyway?

2004 (MBX Lite) = 1M Tris/sec
2005 (programmable) = 5M Tris/sec

....with the estimated triangle rate scaling up to 40M Tris beyond 2007 (for that mysterious "FIMG" thing).

Sounds more of a prediction than anything and albeit 40M Tris/sec sound way too optimistic IMO in such short notice, I don't see anything underwhelming, rather the contrary. If someone's calculating 1 vertice=1 triangle then of course it's a totally different story.

 

If the image has correct connections, the primitive engine does not have access to main bus. It could indicate primitive part not being programmable or it being quite limited.

well, I thought that mobile stuff could be going faster towards unified architechtures and more raw floating point speed. This is because in mobile you actually have more stuff (that is not visible as floating point operations to user) that needs floating point power. (and right now, flops speed seems to be a one of the biggest problems.)

Also, transistor budgets really would like to idea using new floating point power in more flexible way. (using extra power in compressing video stream could be one example.)

but of course, this is just how I see it and as it is just a opinion, so I might be wrong as well as right.

as said, I see mobile gpus doing lot's of things that they don't do in PC side. there's whole bunch of specialized needs in mobile and they greatly vary depending on target devices. That's why I really don't put much weight on Vertice / Triangle / pixel fill rates. Of course, those are one part but most of the real money is made with other kind of features.

 

As I said I doubt it would be programmable, but those kind of "prediction" diagrams aren't very indicative about anything. I'm sure you've seen it already but here's a block diagram from MBX:

http://www.powervr.com/images/BlockDiagrams/MBX.gif

Depends on the requirements of OGL-ES2.0 I guess and if a unified architecture saves hardware space after all or not; it then would come down to design-decisions. If a vendor isn't bound by API requirements, it's rather irrelevant how it reaches a specific target.

I'm not at all saying or implying that you don't have a point; I'd rather tend to agree, but since transistor budget and die space is a major headache for such small devices opportunities and API definitions should be logically tied by that.

W/o having seen from a layman's POV a unified architecture comparing to a non-unified architecture, I'd result to unsafe predictions.

Uhmmm not entirely true. Today's and future GPUs are more and more moving into the GPGPU direction, for multimedia related functions as one example. Mobile GPUs are the ones and the according APIs are the ones that currently are trying to catch up with PC desktop GPUs as fast as possible and not the other way around. Albeit I'm only guessing here mobile GPUs might have an advantage here in SoCs and especially UMA.

Triangle rate or FLOPs are in my book just an alternative way of interpreting throughput. MBX Lite (since I doubt it would ever be clocked much higher than 80MHz) is low end for the first generation anyway. Clock a MBX at 200MHz and 3M (real) Tris/sec or alternatively 800 MFLOPs/sec and you'll end up with adequate FLOP power for the first generation. TI is according to rumours working already on a 90nm die shrink and if I take the predictions in the SAMSUNG graphs as reliable it would be sensible to expect second generation GPUs to start out at both 130 and 90nm. 5M Tris/sec is merely low end I guess; I wouldn't be surprised if 3x times the throughput for high end chips would be possible.

Low end chips are and will continue to be IMO targeting mostly mobile phones. I doubt SAMSUNG is targeting any other devices in the future either.