Official announcement: Toshiba starts PS3 memory producton.

[Paul]

A poor logic, since external memory is dirt-cheap while eDRAM is expensive....

There is nothing poor about it, use your brain.

When you put e-DRAM on a IC you save money in the long run compared to external memory as Sony can control production costs of the entire IC memory included, they don't have as much control over the PS3's XDR memory. Remember, Sony is thinking in the long run with all of this, e-DRAM also has a much higher performance over External.

 

[Deadmeat]

...

When you put e-DRAM on a IC you save money in the long run compared to external memory as Sony can control production costs of the entire IC memory included, they don't have as much control over the PS3's XDR memory.

What is the cost of implementing a 64 MB eDRAM macro cell??? $200? $300? Why even bother when you can purchase external devices for $10~15 a piece???

Why do you think SCEI put only 8 MB of system eDRAM in PSP despite developer criticism??? eDRAM is expensive, anyway you cut it.

 

[marconelly!]

Exactly my point. Both PSX2 and PSP are memory deficient, so I doubt the PSX3 will change this trend.

So do I, but having just 256MB is already kinda defficient if you ask me. 128MB would be crazy low. Anyways, now I see what you meant, so it's beyond the point.

The problem is that we still have no idea how many cell chips there will be in the PS3. Could it happen that they even use just one memory chip per cell, and have four cells, or use two chips and have two or four cells? I was under impression though, that certain amount of memory would be centralized and each cell would have it's own embedded memory. I thought this Toshiba memory would be that centralized RAM.

 

[V3]

If Sony skimps on External memory it's for a reason, this is so they can shove more e-DRAM on instead.

Maybe there is no eDRAM, except for the high bandwidth VRAM in the pixel engine.

Maybe they're going with MCM with upto 16 of the modified version of this module and using 6.4 GHz ones. Who knows, speculation, speculation.

Bijan Davari, vice president of technology and emerging products at IBM Microelectronics, said the Cell architecture would be "scalable, and able to deal with the tradeoffs of performance, power and cost. Our ideas are still evolving, but the elements could be used in ways which are optimal, depending on which box they are used for. The same elements used for a handheld could be multiplied tenfold for ICs aimed at home entertainment systems. One or more chips could be used in a package, depending on the application."

Davari said the concept is not a VLIW architecture, by today's definition. The basic design would include a processing element, strong floating point, and other basic building blocks. "None of this has been 100 percent decided, but the basic idea is that each chip would have five to 10 different elements."

Though the version of Cell aimed at the 100-nm process technology would not include embedded DRAM on the main processor chip, other chips, including a graphics processor, would include eDRAM, Davari said. Then, as process technology moves to 70-nm and 50-nm design rules, embedded DRAM likely would become practical for the main processing elements, he said.

eDRAM, even the Toshiba ones didn't meet expectation of the projected roadmap for eDRAM density, so who knows.

 

[Paul]

What is the cost of implementing a 64 MB eDRAM macro cell??? $200? $300? Why even bother when you can purchase external devices for $10~15 a piece???

256MB of 3.2Ghz Rambus XDR is going to cost 10-15 dollars? Give me a god damn break, and I don't even think this goes into the liscense costs that Sony will undoubtably have to pay Rambus per memory unit.

Sony putting more e-dram into PS3 than XDR will benefit them in the long run, both in performance and cost.

Are you forgetting all the research and breakthroughs Sony and Toshiba have been making in e-DRAM tech?(think 65 nm) what do you think this is for?

Why do you think SCEI put only 8 MB of system eDRAM in PSP despite developer criticism??? eDRAM is expensive, anyway you cut it.

PSP is a handheld with greater cost, heat and size requirements than a console.

 

[marconelly!]

Why do you think SCEI put only 8 MB of system eDRAM in PSP despite developer criticism???

Why do you think they did that? My guess would be because of speed, and possibly cost efficiency in the long run. There was probably no way they could achieve comparable rendering speeds using external RAM. Although, if the rumors about them changing memory structure are true, the whole speciffications might change.

 

[V3]

Quote:
Why do you think SCEI put only 8 MB of system eDRAM in PSP despite developer criticism???

Why do you think they did that? My guess would be because of speed, and possibly cost efficiency in the long run. There was probably no way they could achieve comparable rendering speeds using external RAM. Although, if the rumors about them changing memory structure are true, the whole speciffications might change.

This is probably why

Power-Cutting eDRAM Macro
Blocks of eDRAM have been incorporated into graphics controllers and other high-performance systems where capacity and system performance were the prime considerations. But, new portable systems that need the density of DRAM but must operate at considerably lower power levels than the graphics systems don't yet have a low-power eDRAM solution. That promises to change, though, thanks to a 32-Mbit eDRAM macro developed by Mitsubishi and Sony. The device trims active power to less than 200 mW when operating at 230 MHz, and standby power to just 125 mW. The companies also developed a 64-Mbit macro.

To achieve the low power drain, the chip's designers were able to back off a little on device performance because the intended market—MP3 players, MPEG devices, and other small handheld devices—wasn't as performance-critical as, for instance, the laptop graphics market. To reduce performance losses due to operating from a 1-V supply, four levels of copper interconnect and low-resistance poly-metal gates that have a resistance of only 4 W/square are deployed.

 

[marconelly!]

Hmm, so it's the power consumption. However, I don't understand how using eDRAM can negatively impact performance? Or is this eDRAM developed by them simply a different kind of eDRAM that has less performance compared to other, more power consuming types of eDRAM?

 

[V3]

Hmm, so it's the power consumption. However, I don't understand how using eDRAM can negatively impact performance? Or is this eDRAM developed by them simply a different kind of eDRAM that has less performance compared to other, more power consuming types of eDRAM?

Yes this one main priority is on power consumption.

This one is where the main priority is on performance

Targeting high-bandwidth applications required in a 3D graphics engine, the United Memories/Sony design team crafted a 16-Mbit DDR macro that can transfer data at an effective rate of 1.43 GHz on each I/O line. The macro actually clocks at 714 MHz and provides 256 data inputs plus 256 separate data outputs. Its designers employed local read data drivers instead of pass gates to achieve a relatively low active power and fast reads.

These drivers are composed of a three-state NMOS push-pull differential driver with a control input. Each driver has a pair of local read-data lines as inputs and drives a pair of read-data lines. The drivers cut power consumption by reducing the capacitance and signal swing on the nonprecharged local read-data lines. Speed is improved as well because the drivers act as low-impedance buffers between the read amplifier and the read-data lines.

16 of this macro were used @500 MHz to give bandwidth of 512 GB/s and power: 8 W for reads, 11 W for writes, and 18 W for RMW cycles just for the 16 macros.

 

[Deadmeat]

...

However, I don't understand how using eDRAM can negatively impact performance?

The eDRAM fab process itself hurts the speed of logic gates. This is why eDRAM devices don't clock high.

 

[Deadmeat]

...

So do I, but having just 256MB is already kinda defficient if you ask me.

I don't think SCEI bean counters care if you complain or not. Take it or leave it..

Could it happen that they even use just one memory chip per cell, and have four cells, or use two chips and have two or four cells?

Something like that. Each chip is rated 32 GFLOPS(Kutaragi's presentation) and you would have a 128 GFLOPs box if 4 are present.

I was under impression though, that certain amount of memory would be centralized and each cell would have it's own embedded memory.

CELL is a decentralized message passing architecture. Memory is unique and exclusive to each node.

 

[V3]

CELL is a decentralized message passing architecture.

Wow, did you just come up with that name ? Normally you just refer it as distributed memory. But that name kinda cool.

Memory is unique and exclusive to each node.

That's the APUs memory. Up a level, its more of distributed-shared memory.

 

[Wunderchu]

Re: ...

Toshiba First to Commercialize 512-megabit XDR DRAM; 3.2GHz Data Transfer Speed is the Fastest of Any Memory Device

TOKYO--(BUSINESS WIRE)--Dec. 24, 2003--Toshiba Corporation (Pink Sheets: TOSBF; OTHER OTC: TOSHF) today announced that it had started to sample 512-megabit XDR(TM) DRAMs with a data transfer speed of 3.2GHz, the world's fastest speed of any memory device. XDR DRAMs are designed for high-performance broadband applications, including digital consumer electronics, network systems and graphic systems.
The XDR DRAM is based on Rambus's XDR memory interface technology and offers Octal Data Rate, which transfer eight data per one clock cycle and offers eight times the bandwidth of today's best-in-class PC memory.

Toshiba today made available samples of three versions of the new ultra high performance memory, TC59YM916AMG32A, TC59YM916AMG32B, TC59YM916AMG32C.

Next-generation broadband applications will process large volumes of data at higher speed in real time and will require large-volume, ultra high-speed memory chips. Toshiba meets these needs with its XDR DRAMs.

"Toshiba has been playing a leadership role in realizing XDR DRAM technology," said Shozo Saito, Technology Executive of Semiconductor Company at Toshiba Corporation. "In October 2002, we were first to license Rambus's most advanced technologies, and we have promoted their development ever since. Our efforts have borne fruit, as we are first in the world to sample XDR DRAM, and do so well ahead of our original schedule. The start of sample shipments of first generation XDR DRAM is a significant step to supply high-performance products for our customers. We aim for mass production in 2005, and to secure our leading position in this business area."

"We are pleased that Toshiba has delivered the first XDR DRAM samples ahead of schedule. Toshiba has taken the first step in providing the market with high-quality, cost-effective XDR DRAMs for the next-generation of innovative broadband products," said Laura Stark, vice president of the Memory Interface Division at Rambus. "We've shared a long and mutually beneficial relationship with Toshiba and look forward to continuing our work with them in making XDR DRAM a success in the marketplace."


Major Specifications

Model Numbers: TC59YM916AMG32A; TC59YM916AMG32B; TC59YM916AMG32C

Configuration: 4 megabits word x 8 banks x 16 bits

Max. Data Rate: 3.2 Gbps

Cycle Time: 40 nanoseconds; 50 nanoseconds; 60 nanoseconds

Power Supply: 1.8V VDD

Interface: DRSL (Differential Rambus Signaling Level)

Latency: 27 nanoseconds; 35 nanoseconds; 35 nanoseconds

Package Size: 1.27 x 0.8mm pitch BGA


Note: XDR is a trademark or registered trademark in Japan and/or other counties.

English press release...

I am interested in those Cycle Time numbers ... to me that sounds like MHz ?

40 ns = exactly 25 MHz ........... so, to achieve that 3.2 Gbps data rate, the RAM would need a super high bit rate ( 1152 bit, to be exact ) ???

... does what I am speculating make any sense ?

 

[akira888]

EDRAM capacity doesn't "boost" external RAM's capacity. The reason for this is that EDRAM is used as a cache or scratchpad and any data contained within it is likely also present in XDR. In other words boosting EDRAM will do absolutely nothing to alleviate a potential shortage of XDR.

 

[nAo]

EDRAM capacity doesn't "boost" external RAM's capacity. The reason for this is that EDRAM is used as a cache or scratchpad and any data contained within it is likely also present in XDR. In other words boosting EDRAM will do absolutely nothing to alleviate a potential shortage of XDR.

Pretty wrong.
eDRAM is just...memory! you can use it to replicate data also contained in external memory, bu you can also use it to store whatever you want.
Imagine a 3D engine that stores some base mesh for a character model in the external ram that is DMAed into eDRAM.
One APU could DMA pieces of this base mesh into its local SRAM and start to tesselate it using subdvision surfaces, the results are DMAed out to eDRAM where a second APU stream that data into its local SRAM to perform other calculation such displacement mapping or skinning.
This second APU store out in the eDRAM the final geometry that is ready to be rasterized by the visualizer...and so on..
In another case one APU could generate some procedural texture or geometry directly into the eDRAM without having base information stored in the external ram and duplicated into the eDRAM.

ciao,
Marco

 

[Paul]

The patent Broadband Engine has SRAM(I am certain it is SRAM) for Cache and APU code(APU's have 128kb each, around 4mb total for the whole BE), the e-DRAM is ram for anything you want.

 

[akira888]

EDRAM capacity doesn't "boost" external RAM's capacity. The reason for this is that EDRAM is used as a cache or scratchpad and any data contained within it is likely also present in XDR. In other words boosting EDRAM will do absolutely nothing to alleviate a potential shortage of XDR.

Pretty wrong.
eDRAM is just...memory! you can use it to replicate data also contained in external memory, bu you can also use it to store whatever you want.
Imagine a 3D engine that stores some base mesh for a character model in the external ram that is DMAed into eDRAM.
One APU could DMA pieces of this base mesh into its local SRAM and start to tesselate it using subdvision surfaces, the results are DMAed out to eDRAM where a second APU stream that data into its local SRAM to perform other calculation such displacement mapping or skinning.
This second APU store out in the eDRAM the final geometry that is ready to be rasterized by the visualizer...and so on..
In another case one APU could generate some procedural texture or geometry directly into the eDRAM without having base information stored in the external ram and duplicated into the eDRAM.

That's true. I was referring to the fact that, in general, adding memory to levels higher in the heirarchy doesn't aid you below. And while your example certainly is valid (real-time geometry generation) my argument was more along the lines that most data will have to be replicated, and most data still isn't procedurally generated and likely won't be for at least a while.

Just out of curiousity, since you mentioned subdiv surfaces: how realistic are these for use in a console since they require access to neighboring vertices' data in order to refine (and generate new) vertices. I remember reading about PN trianges (aka TRUFORM) and how that worked because it generated its' seven Bezier control points with nothing except the normals and positions of the triangle that was in the tesselation unit at that time. I don't see how for example the Loop subdiv algorithm, which needs 4 vertices' data to generate a new vertex, and all of its' incident neighbors to refine a vertex, could fit in the "standard pipeline."

 

[passerby]

I think that in general, besides a fast cache/scratchpad, EDRAM will be important for dealing with crtical regions in a parallel application.

Back to the 512MBit question. Will this indicate that 512MBit modules will be deployed instead of traditional 64MB/128MB module configuration. Any significance of this implementation?

Anyway, we can safely let go of any suggestions of a late 2006/2007 debut for Sony's next gen console entry, as discussed a few weeks ago. A late 2005 Japanese launch is looking very likely at this point.

 

[nAo]

.. my argument was more along the lines that most data will have to be replicated, and most data still isn't procedurally generated and likely won't be for at least a while.

I partialy agree with you, but if you had been writing most data instead of any data ..

Just out of curiousity, since you mentioned subdiv surfaces: how realistic are these for use in a console since they require access to neighboring vertices' data in order to refine (and generate new) vertices. I remember reading about PN trianges (aka TRUFORM) and how that worked because it generated its' seven Bezier control points with nothing except the normals and positions of the triangle that was in the tesselation unit at that time. I don't see how for example the Loop subdiv algorithm, which needs 4 vertices' data to generate a new vertex, and all of its' incident neighbors to refine a vertex, could fit in the "standard pipeline."

Fastest (and accurate too) subdvision surface generation algorithms don't need to access to neighbour vertices, each triangle of the base mesh is processed and subdivided in a pretty streamlined fashion...
And that could be true for vertices of any valence, in the general case you may need more of 4 vertices to generate a new one..
PS3 will probably be a very good platform to perform such tasks...

ciao,
Marco

 

[Vince]

eDRAM, even the Toshiba ones didn't meet expectation of the projected roadmap for eDRAM density, so who knows.

Whoa... where did you get this from? If you're referring to what I believe you are, entire industry is moving to the 90-65-45 steppings. The Toshiba eDRAM is better than the industry mean for the 65nm node - so I really don't see how this is relevant when you consider that it's highly probable that any IC in the PS3 was designed with the 65nm node in mind; it's intrinsically related to the capabilities on that process. Not a circa-1999/2000 projection that the entire industry has migrated from. Besides, the absolute difference is negligible. This sounds more like an arguing point I'd expect out of DM than your quality.