Official announcement: Toshiba starts PS3 memory producton.

How does the memory clock relates to the overall system clock?

2 probable, 4 maximum. Beyond that the cost gets out of control.
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You think that it's 'probable' that PS3 will have 128MB of main memory? I think that's higly improbable that they will put just 4x as much main memory as they had in PS2. That's the same probabilty as if they were going to put 8MB in PS2...

Then again, if anyone told me a year ago that Sony would be making a handheld for the end of 2004 that will be capable of pushing 32Mpolys/sec but would have only 8MB of RAM, I would be laughing as well. Sony are just weird when it comes to memory.

That just makes me wonder what 512Mbit refers to. Storage? A strange number since it converts to 61.03MB.
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Mbits are standard unit for memory capacity. One byte has eight bits, so 512Mbits converts to 64Mbytes.
 
Heh ! May be that sentense is a bit misleading.

The sentense said the data read/write will be 8 times of the previous

But previous is 400MHz bus DDR, now 3.2GHz without DDR for XDR ?

If so, 4 modules will only be 25.6GB/s.

May be they will be using wider modules.
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25.6 GB/s is 8 times 3.2 GB/s ;)
 
Re: ...

Edited a bit to make it more complete.

maskrider said:
" 製品化したのはデータの読み書き速度が従来の８倍の毎秒3.2ギガヘルツと高速で"
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Well, I don't claim to have great Japanese, but doesn't say "... according to the spec sheet, its data read speed is eight times faster than before, for a speed of 3.2 GHz"? The word used is "ギガヘルツ" (gigahertz), which refers to clockspeed and not data rate. I know this might be weird because they're talking about "読み書き速度" (lit. data read speed), but I still think they are referring to they actual GHz rather than Gb/s.

Divide by 8, and you get 400Mhz, the "previous speed" - DDR 400 ring a bell? And of course, it is completely consistent with what V3 wrote.

V3 said:
For example, a single, 2-byte wide, 3.2 GHz XDR DRAM component provides up to 6.4 GB/sec bandwidth over the XDR Interconnect
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Sorry DMGA, I think you'll need to try again. The bandwidth is 3.2GHz*bus width (16? 32? 64? 128?)

Oh, yeah, Merry Christmas.
 
V3 said:
Heh ! May be that sentense is a bit misleading.

The sentense said the data read/write will be 8 times of the previous

But previous is 400MHz bus DDR, now 3.2GHz without DDR for XDR ?

If so, 4 modules will only be 25.6GB/s.

May be they will be using wider modules.
Click to expand...

25.6 GB/s is 8 times 3.2 GB/s ;)
Click to expand...

Heh ! If they are referring to the machines, then it is. :D

But they seem to be referring to the chip only. :?
 
Re: ...

nondescript said:
maskrider said:
" 製品化したのはデータの読み書き速度が従来の８倍の毎秒3.2ギガヘルツと高速で"
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Well, I don't claim to have great Japanese, but doesn't say it is eight times faster than previous [things], which is 3.2 GHz. The word used is "ギガヘルツ" (gigahertz), which refers to clockspeed and not data rate.

Divide by 8, and you get 400Mhz - DDR 400 ring a bell? And of course, it is completely consistent with what V3 wrote.
Click to expand...

I knew that and understood that before I post my first followup, it says "Data read/write is 8 times the past running at 3.2GHz".
 
...

You think that it's 'probable' that PS3 will have 128MB of main memory?
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Per chip. Have 4 CELL chips per PSX3 board and you would have 512 MB in total. Although I doubt PSX3 would have more than 256 MB, so its more like 1 CELL chip + 1 XDR RAM = 1 CELL node... This is what that SCEI MCM patend described.

Then again, if anyone told me a year ago that Sony would be making a handheld for the end of 2004 that will be capable of pushing 32Mpolys/sec but would have only 8MB of RAM, I would be laughing as well. Sony are just weird when it comes to memory.
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Exactly my point. Both PSX2 and PSP are memory deficient, so I doubt the PSX3 will change this trend.
 
...

Toshiba First to Commercialize 512-megabit XDR DRAM; 3.2GHz Data Transfer Speed is the Fastest of Any Memory Device

TOKYO--(BUSINESS WIRE)--Dec. 24, 2003--Toshiba Corporation (Pink Sheets: TOSBF; OTHER OTC: TOSHF) today announced that it had started to sample 512-megabit XDR(TM) DRAMs with a data transfer speed of 3.2GHz, the world's fastest speed of any memory device. XDR DRAMs are designed for high-performance broadband applications, including digital consumer electronics, network systems and graphic systems.
The XDR DRAM is based on Rambus's XDR memory interface technology and offers Octal Data Rate, which transfer eight data per one clock cycle and offers eight times the bandwidth of today's best-in-class PC memory.

Toshiba today made available samples of three versions of the new ultra high performance memory, TC59YM916AMG32A, TC59YM916AMG32B, TC59YM916AMG32C.

Next-generation broadband applications will process large volumes of data at higher speed in real time and will require large-volume, ultra high-speed memory chips. Toshiba meets these needs with its XDR DRAMs.

"Toshiba has been playing a leadership role in realizing XDR DRAM technology," said Shozo Saito, Technology Executive of Semiconductor Company at Toshiba Corporation. "In October 2002, we were first to license Rambus's most advanced technologies, and we have promoted their development ever since. Our efforts have borne fruit, as we are first in the world to sample XDR DRAM, and do so well ahead of our original schedule. The start of sample shipments of first generation XDR DRAM is a significant step to supply high-performance products for our customers. We aim for mass production in 2005, and to secure our leading position in this business area."

"We are pleased that Toshiba has delivered the first XDR DRAM samples ahead of schedule. Toshiba has taken the first step in providing the market with high-quality, cost-effective XDR DRAMs for the next-generation of innovative broadband products," said Laura Stark, vice president of the Memory Interface Division at Rambus. "We've shared a long and mutually beneficial relationship with Toshiba and look forward to continuing our work with them in making XDR DRAM a success in the marketplace."


Major Specifications

Model Numbers: TC59YM916AMG32A; TC59YM916AMG32B; TC59YM916AMG32C

Configuration: 4 megabits word x 8 banks x 16 bits

Max. Data Rate: 3.2 Gbps

Cycle Time: 40 nanoseconds; 50 nanoseconds; 60 nanoseconds

Power Supply: 1.8V VDD

Interface: DRSL (Differential Rambus Signaling Level)

Latency: 27 nanoseconds; 35 nanoseconds; 35 nanoseconds

Package Size: 1.27 x 0.8mm pitch BGA


Note: XDR is a trademark or registered trademark in Japan and/or other counties.
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English press release...
 
Per chip. Have 4 CELL chips per PSX3 board and you would have 512 MB in total. Although I doubt PSX3 would have more than 256 MB, so its more like 1 CELL chip + 1 XDR RAM = 1 CELL node... This is what that SCEI MCM patend described.
Click to expand...

I actually speculate along that line too.
 
Heh, sorry Maskrider, I changed the post while you were replying, after I realized it could be read both ways. I think what you're saying is:

3.2 GHz is the previous speed, we are 8 times faster.

Anyways, that's the impression I got from reading your first post:
Maskrider said:
The PS2 is using 2 pieces of PC800 RDRAM (2 channels, one per channel), which gives the system 3.2GB/s memory bandwidth (1.6GB/s per chip). The transfer is 16bit based per chip.

The new memory is 8 times the old transfer rate, that means 12.8GB per chip.
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If PS3 would be using 4 of them, the bandwidth will be 51.2GB/s.

What I'm saying is:

3.2 Ghz is the current speed, which is 8 times faster than the previous speed.
 
Re: ...

Configuration: 4 megabits word x 8 banks x 16 bits
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With 8 banks per module should be possible to keep 8 pages opened at time per module, shared between all the modules. A good memory accesses manager could hide a lot of latency scheduling ahead pages opening....
We have to remember that XDR tech use differential signaling, so a 16 bit wide module would have a 32 lines wide data bus.

ciao,
Marco
 
3.2 Ghz is the current speed, which is 8 times faster than the previous speed.
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Edit: Previous speed is 800 MHz Well its 200 MHz QDR, this 3.2 GHz is actually 400 Mhz ODR.
 
nondescript said:
Heh, sorry Maskrider, I changed the post while you were replying, after I realized it could be read both ways. I think what you're saying is:

3.2 GHz is the previous speed, we are 8 times faster, so it is 25.6Ghz

What I'm saying is:

3.2 Ghz is the current speed, which is 8 times faster than the previous speed.
Click to expand...

I mean from that sentense, "the new data rate is 8 times the old and is now running at 3.2GHz".

That's why I think it can be ambiguous.
 
V3 said:
3.2 Ghz is the current speed, which is 8 times faster than the previous speed.
Click to expand...

Previous speed is 800 MHz Well its 400 MHz DDR, this 3.2 GHz is actually 800 Mhz QDR.
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Talking about the translation, and not really about any factual truth... ;)

Maskrider said:
That's why I think it can be ambiguous.
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Yeah, I agree. Anyways, the matter is pretty much resolved with the English press release. The new chip has 3.2 GHz data transfer speed.
 
You think that it's 'probable' that PS3 will have 128MB of main memory? I think that's higly improbable that they will put just 4x as much main memory as they had in PS2. That's the same probabilty as if they were going to put 8MB in PS2...
Click to expand...

Everyone is forgetting that PS3 is a late 2005/maybe 2006 device..

And there is no way that the leap in memory size from psone to ps2(TOTAL SYSTEM) will be bigger than the one from ps2 to ps3. And no you can't say "sony does this stuff..." because the chances of this happening are just dismal.

If Sony skimps on External memory it's for a reason, this is so they can shove more e-DRAM on instead.
 
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