Official announcement: Toshiba starts PS3 memory producton.

The cool news just in time before I leave for my holliday vacation. :p

Before people jump to conclusions about what the minimum amount of memory for PS3 is - I would like to correct a "minor" fault in translation - the modules are 512Mbit.
Since they are dubbed sample I will refrain from making any guesses though (sample could still mean a great many things including an overestimation).

Anyway, I am feeling like fooling around a bit today (and possibly evading this thread going down the wrong path) so here's a little joke - a few suggestions for what various B3D posters will have to say about it... (I leave you to guess who is who yourself).

This falls flat in line with my predictions of the monster PS3 will be. Not only will it be incredibly difficult to program, Sony now made the same mistake as with PS2 by using overpriced and underperforming Rambus technology to artificially inflate spec but will ultimately result in worse overall performance and a system hampered by having only 2x the amount of memory of a 4 year old Microsoft console.
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:) :) If samples are in production by now, this surely means good things for 2005 launch, and it looks like my wishes for 512MB (4 modules isn't a lot, PS2 already had 2) came true also. Combined with 64MB edram and all the memory saving techniques like procedural rendering and Reyes this will be more then enough for great things. ;)
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Memory schmemory. PS3 - some more assembly required
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Only kidding guys, don't lynch me ;)
Merry Christmas!
 
Thanks for pointing out the careless translation. That just makes me wonder what 512Mbit refers to. Storage? A strange number since it converts to 61.03MB. Or is this a common and accepted sample storage size? Bandwidth? Speed? Anyone clarify?
 
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Faf is correct that this is a 64 MB x 3.2 Ghz device.

The question is, how many will SCEI use in PSX3???

If 2 are used as in PSX2, then the memory capacity is 128 MB @ 12.8 GByte/s.

If 4 are used, then the capacity grows to 256 MB @ 25.6 Gbyte/s

Either way, this is a very unimpressive figure for a chip that is supposed to do a teraflop, and already outperformed by most DX9 GPUs.

1_multipart_xF8FF_5_XDR_sys_top_lg.jpg
 
256 MB is an absolute minimum amount for the main external memory. developer may even as Sony for more, like they did with PS1 back in 1994, and are doing now with PSP. Especially if Sony is thinking about putting in only 128 MB.
 
Re: ...

Deadmeat said:
Faf is correct that this is a 64 MB x 3.2 Ghz device.

The question is, how many will SCEI use in PSX3???

If 2 are used as in PSX2, then the memory capacity is 128 MB @ 6.4 GByte/s.

If 4 are used, then the capacity grows to 256 MB @ 12.8 Gbyte/s

Either way, this is a very unimpressive figure for a chip that is supposed to do a teraflop, and already outperformed by most DX9 GPUs.
Click to expand...

The PS2 is using 2 pieces of PC800 RDRAM (2 channels, one per channel), which gives the system 3.2GB/s memory bandwidth (1.6GB/s per chip). The transfer is 16bit based per chip.

The new memory is 8 times the old transfer rate, that means 12.8GB per chip.

If PS3 would be using 4 of them, the bandwidth will be 51.2GB/s.
 
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256 MB is an absolute minimum amount for the main external memory.
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Not if CELL is really dirt-cheap(say $30 a part) and SCEI is planning to use multiple CELL chips in PSX3.

PSP Vs PSX3

2.6 GB/s for 2.6 GFLOPS vs ( 12.8 GB/s for 12.8 GFLOPS or 25.6 GB/s for 25.6 GFLOPS ) ???

Kutaragi wasn't BShitting when he showed that he would use 64 CELL chips to build a 2 TFLOPS board; individual CELL chips aren't all that but SCEI is selling on the aggregated power of CELL.
 
Re: ...

Deadmeat said:
If 2 are used as in PSX2, then the memory capacity is 128 MB @ 6.4 GByte/s.

If 4 are used, then the capacity grows to 256 MB @ 12.8 Gbyte/s

Either way, this is a very unimpressive figure for a chip that is supposed to do a teraflop, and already outperformed by most DX9 GPUs.

1_multipart_xF8FF_5_XDR_sys_top_lg.jpg
Click to expand...
We don't know the final clock and number of modules figure so it's not the case to make such extreme speculations.
The external memory will not have a huge bandwith anyway if PS3 architecture will be similar to the architecture described by some Sony patent. There is a memory hierarchy composed of 3 layers, and this should be the slower.

ciao,
Marco
 
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We don't know the final clock
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Surely you do, this is an XDR standard, remember???

and number of modules figure
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2 probable, 4 maximum. Beyond that the cost gets out of control.

Anyway you put it, 6.4 GB/s or 12.8 GB/s is not large enough to support significant FLOP rating, you are looking at the max flop rating of 32 GFLOPS/chip at most using the XDR architecture.

While that sounds unimpressive, delivering this FLOPS at $30 is actually impressive, no other architecture delivers GFLOPS/dollar.
 
Re: ...

Deadmeat said:
The new memory is 8 times the old transfer rate, that means 12.8GB per chip.
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Says who? You??? Rambus doesn't claim that.
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From that article in Bloomberg.co.jp, I can read the Japanese.

" 製品化したのはデータの読み書き速度が従来の８倍の毎秒3.2ギガヘルツと高速で"
 
Not if CELL is really dirt-cheap(say $30 a part) and SCEI is planning to use multiple CELL chips in PSX3.

PSP Vs PSX3

2.6 GB/s for 2.6 GFLOPS vs ( 6.4 GB/s for 6.4 GFLOPS or 12.8 GB/s for 13.8 GFLOPS ) ???

Kutaragi wasn't BShitting when he showed that he would use 64 CELL chips to build a 2 TFLOPS board; individual CELL chips aren't all that but SCEI is selling on the aggregated power of CELL.
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Your forgetting that Toshiba and Sony are building the Broadband Engine and it is going to use Redwood and XDR in accordance with the Toshiba, SCEI, Rambus contract?

anyway, 256mb is fine concidering Sony plans to shove what looks like a good chunk of fast e-DRAM on both BE and VS.
 
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It's a scalable standard.
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Sure, 8~64 bit width, 3.2 Ghz or 6.4 Ghz.(3.2 ~ 52.8 GB/s)

Save for the fact that the 6.4 Ghz part doesn't exist and is too costly for PSX3 implementations.
 
Re: ...

Deadmeat said:
It's a scalable standard.
Click to expand...
Sure, 8~64 bit width, 3.2 Ghz or 6.4 Ghz.(3.2 ~ 52.8 GB/s)

Save for the fact that the 6.4 Ghz part doesn't exist and is too costly for PSX3 implementations.
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A 16 bit width per module at 3.2 Ghz with 4 modules would be a very nice set up for a bottom-hierarchy memory.
Remember Deadmeat I'm just speculating, I'm noy saying I'm right and you're wrong..but please, don't lay down speculations as facts ;)
We all want this forum to be a place where everyone can share his vision, not a place where flamewars born and die as fast as stars in the sky.

ciao,
Marco
 
If 2 are used as in PSX2, then the memory capacity is 128 MB @ 6.4 GByte/s.

If 4 are used, then the capacity grows to 256 MB @ 12.8 Gbyte/s
Click to expand...

From Rambus XDR Technology Summary

For example, a single, 2-byte wide, 3.2 GHz XDR DRAM component provides up to 6.4 GB/sec bandwidth over the XDR Interconnect
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Its 16 bit per module. If they are going to use 4 module, it will be 64 bit, which is not bad, compare to nasty 256 bit bus.

Edit: Of course except cost, nothing stopping them from going with 256 bit bus.

Merry Christmas everyone.
 
V3 said:
If 2 are used as in PSX2, then the memory capacity is 128 MB @ 6.4 GByte/s.

If 4 are used, then the capacity grows to 256 MB @ 12.8 Gbyte/s
Click to expand...

From Rambus XDR Technology Summary

For example, a single, 2-byte wide, 3.2 GHz XDR DRAM component provides up to 6.4 GB/sec bandwidth over the XDR Interconnect
Click to expand...

Its 16 bit per module. If they are going to use 4 module, it will be 64 bit, which is not bad, compare to nasty 256 bit bus.

Edit: Of course except cost, nothing stopping them from going with 256 bit bus.

Merry Christmas everyone.
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Heh ! May be that sentense (bloomberg) is a bit misleading.

The sentense said the data read/write will be 8 times of the previous

But previous is 400MHz bus DDR, now 3.2GHz without DDR for XDR ?

If so, 4 modules will only be 25.6GB/s.

May be they will be using wider modules.
 
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