Nvidia's Hybrid SLI

[Arun]

After a bit of thinking, I figured that the feature differences could be large enough to justify two chips. These specs are obviously partially speculation but they should give you a rough idea...

MCP72
2x8 PCIe Gen2
3x1 PCIe Gen2
6 SATA/2 PATA
2xHT3.0 Ports+ (for servers)
2xGbE MACs? (usage optional)
12xUSB+

MCP78
1x16 PCIe Gen2(?)
3x1 PCIe Gen2(?)
4 SATA/1 PATA
1xHT3.0 Port
1xGbE MAC
12xUSB

Other possibilities include:
- MCP72 IGP being slower than MCP78's (since it'll be paired with faster GPUs anyway...)
- MCP72 having other misc. features (RAID acceleration?)
- MCP78 only being x8 Gen2/x16 Gen1.
- MCP78 only having 2x1 PCIe Gen2 ports.
- MCP78 having less legacy functionality for cost reasons.

It is also possible that MCP78 is now a 55nm design - back at Analyst Day, Jen-Hsun said that it would be made on 65nm *or* 55nm. If it got delayed to Q108 while MCP72 wasn't, while the design is so similar, this would be a rather logical justification.

 

[AnarchX]

Hmm, well AFAICT:
- 750a is MCP72.
- 780a is MCP72+BR04.
- 750i is MCP72+C55.
- 780i is MCP72+C55+BR04.
- 790i is MCP72+C73.
.

Seems to be MCP55+C55+BR04:
http://news.expreview.com/2007-09-29/1191064136d3816.html

Could BR04 really offer PCIe2.0-lanes?

 

[Arun]

Seems to be MCP55+C55+BR04:

Okay for C55+BR04, but I can't read the chip's label saying MCP55, and I don't see where that is in the text? Once again, if I am missing something, please let me know!

Could BR04 really offer PCIe2.0-lanes?

Yes, this would likely reduce the maximum CPU-GPU bandwidth, but GPU-GPU bandwidth would be unaffected. Unless they're doing something more complex than I'm thinking of, this is a decent compromise, and I'm not sure how you could do better while still using C55 anyway...

Anyway, even if that board is MCP55, may I point out that the CeBit MCP73 boards were anything but using MCP73 chips? It could just be a prototype to test BR04 and not a production board for all we know, but it is indeed very suspicious.

 

[Arun]

Okay, so I just measured the different chips on that leaked picture assuming it's an ATX board, which it kinda obviously is:
BR04: 8.6x5.0 = 43.0mm2
C55: 10.1x7.6 = 77.8mm2
MCP: 12.0x8.8 = 105.6mm2

Sadly, I don't have MCP55's die size. Keeping in mind it's a 130nm chip, that size isn't completely impossible. But at the same time, it should be noted that a 105.6mm2 65nm chip would be more than big enough for a G8x/G9x-based IGP in addition to the southbridge.

It is certainly interesting, however, that there is no DVI/HDMI/VGA output whatsoever on this board. As such, either it doesn't have an IGP, or MCP72 does have an IGP but without output functionality. This would only make sense if G8x/G9x could shutdown the entire GPU and memory except PCI Express/Output. That would be a wonderfully elegant solution, but allow me to have my doubts here...

Once again, it should also be considered that this might only be a prototype board. Sigh.

EDIT: Upon further analysis, it turns out that board's MCP has the *exact* same width/height ratio as MCP55, so it does seem very unlikely to be MCP72 or any other MCP... Strange! Once again, it would be nice to be sure it was a final production board.

 

[AnarchX]

Some stuff about MCP79:

http://www.hkepc.com/?id=176&page=3

 

[Arun]

Hmm, earlier rumours were that MCP79 was DDR2 dual-channel. Now it's DDR3 single-channel? Meh. That'd okay design decision for notebooks (lower power for a given amount of bandwidth), but a godawful one for desktops where the majority of the money probably is.

 

[AnarchX]

What do you think about the structure of the IGP in MCP72/78/79?

Performance-target should be ~8400GS, like supposed in the H-SLI-slides.

Could it be a full G98(~G86 with 64Bit MC) or it is possible that NV cut it down to 4TA/TFs+1Vec8-ALU and run it on 0.9/1.9GHz? (MCP73 runs already on 600MHZ@80nm and N68@90nm reached 999MHz with passive heat-sink @OC)

 

[Arun]

Hmm. I guess that's really a question of scalability; would they gain much from halving the number of TAs/SPs? My guess is no. That, and what they probably want is G98-level performance, not G86-level performance. At least that's my guess, heh.

 

[ShaidarHaran]

Hmm, earlier rumours were that MCP79 was DDR2 dual-channel. Now it's DDR3 single-channel? Meh. That'd okay design decision for notebooks (lower power for a given amount of bandwidth), but a godawful one for desktops where the majority of the money probably is.

How do you figure? Last time I checked Intel was stuck @ 1333MHz FSB, which pairs up quite nicely with a single channel of 1333MHz DDR3. Dual-channel is overkill right now, and will remain so until Intel abandons the FSB. Technically speaking, of course. From a marketing standpoint it's not such a great idea, but in the real world it won't make a bit of difference.

 

[Arun]

How do you figure? Last time I checked Intel was stuck @ 1333MHz FSB, which pairs up quite nicely with a single channel of 1333MHz DDR3. Dual-channel is overkill right now, and will remain so until Intel abandons the FSB. Technically speaking, of course. From a marketing standpoint it's not such a great idea, but in the real world it won't make a bit of difference.

Sure, for CPU-only workloads. But we're talking about an IGP here, so with 1333MHz DDR3 and full FSB utilization, you'd have a grand total of 0 bits/second left for the GPU... This is, of course, assuming that both links are exactly as efficient - but you get my point.

 

[ShaidarHaran]

Sure, for CPU-only workloads. But we're talking about an IGP here, so with 1333MHz DDR3 and full FSB utilization, you'd have a grand total of 0 bits/second left for the GPU... This is, of course, assuming that both links are exactly as efficient - but you get my point.

Ah, good point. I'd completely forgotten about the IGP aspect

 

[Arun]

As if this wasn't confusing enough already: http://www.digitimes.com/mobos/a20071002PD215.html

So, according to Digitimes, MCP72 is an IGP... that is pin-compatible to a non-IGP chipset... Errr! If this had to be taken literally, it would seem to confirm the notion of an output-less IGP.

This implies that during Hybrid SLI, the PCI Express controllers on the discrete GPU are still active, as well as the analog/output parts, but everything else is shutdown. This would be a wonderfully elegant way to handle multi-monitor Hybrid SLI and plain SLI, but it does require hardware support...

So for now, call me skeptical about this. But it'd be very interesting if it turned out to be true, obviously.

EDIT: And there would be no bandwidth limitation to do this either, since output bandwidths are in gigabits/s and PCI Express bandwidths are in gigabytes/s...

 

[AnarchX]

This implies that during Hybrid SLI, the PCI Express controllers on the discrete GPU are still active, as well as the analog/output parts, but everything else is shutdown. This would be a wonderfully elegant way to handle multi-monitor Hybrid SLI and plain SLI, but it does require hardware support...

But this slide states, there will be outputs on mainboard:

And with your idea, the card-power-source has to be still active, which means some consumption, since these are not very high efficient.

I think this:

An advantage of the MCP72P is that it is pin compatible with the previous MCP65 chipsets, therefore motherboard makers should only need to make small modifications to their PCB designs helping to save costs, added the sources.

.... means only there could be a 750a-version without H-SLI.

 

[AnarchX]

Digit-Life has some pictures of 780a reference-board and MCP72 without cooler on a 790i-board:
http://www.digit-life.com/articles2/video/g92-part1-page1.html

 

[Arun]

Digit-Life has some pictures of 780a reference-board and MCP72 without cooler on a 790i-board:
http://www.digit-life.com/articles2/video/g92-part1-page1.html

Based on the chip's positioning on the motherboard and what I can read on it, that's not MCP72, that's the new DDR2/DDR3 memory controller...

Anyway I can't help but feel NVIDIA's roadmap for Intel is kinda subpar. On the AMD side, you have MCP72 as 750a and 780a, while on the Intel side you have some rather ridiculous and expensive chip combinations. 750i as MCP72+C55 and 780i as MCP72+C7x would have made so much more sense (financially and for consumers), ah well...

I still don't really understand why NVIDIA can release MCP72 alone today but not MCP72+C55, which would make a better 750i until the new high-end comes out in January. Now, AFAICT, we have MCP51+C55+BR02 for the 750i, which is just ridiculous. Seems to me like these BR02-based configs were expected to be released a few months ago and it didn't happen, meh.

 

[INKster]

Based on the chip's positioning on the motherboard and what I can read on it, that's not MCP72, that's the new DDR2/DDR3 memory controller...

Anyway I can't help but feel NVIDIA's roadmap for Intel is kinda subpar. On the AMD side, you have MCP72 as 750a and 780a, while on the Intel side you have some rather ridiculous and expensive chip combinations. 750i as MCP72+C55 and 780i as MCP72+C7x would have made so much more sense (financially and for consumers), ah well...

I still don't really understand why NVIDIA can release MCP72 alone today but not MCP72+C55, which would make a better 750i until the new high-end comes out in January. Now, AFAICT, we have MCP51+C55+BR02 for the 750i, which is just ridiculous. Seems to me like these BR02-based configs were expected to be released a few months ago and it didn't happen, meh.

The "BR02" was a PCIe-AGP bridge (and vice-versa), not a PCIe 2.0 controller chip.
I think you meant to say "BR04", right ?


Personally, i think they did the right call.
It will only truly make sense to develop brand new motherboard chipsets for Intel CPU's once either PCIe 2.0 is well established or "Nehalem" comes along (whichever comes first).
The 790i SLI/C73 is a case apart since it's strictly focused on the High-End (the exclusive DDR3 support is reason enough), therefore it's a niche, high-margin product.

 

[AnarchX]

MCP78 pictured.

http://my.ocworkbench.com/bbs/showthread.php?p=422772#post422772

 

[Arun]

125-130mm2 given the coin is supposed to have a diameter of 26mm and the package is supposedly 24.5x24.5... That's one hell of a big IGP, probably only slightly more than 450 chips per 300mm wafer! :|

 

[AnarchX]

Sure it is big, but it is an one-chip-solution and probadly include a GF8400-class-IGP, which will convince imo some OEMs.

 

[Twinkie]

Sure it is big, but it is an one-chip-solution and probadly include a GF8400-class-IGP, which will convince imo some OEMs.

That would be quite the IGP. Packing video capabilities/performance far superior to intel's, it also packs DX10 albeit not really usable though.