NVidia Tegra ULP GeForce Speculation

As for small triangles, I wonder what SGX is doing different than the MBX to improve peak tri rates per MHz?

I thought that the MBX was a 32x32 pixel tile size with a parallel 32x1 pixel tile line of parallel triangle equation and depth test per clock. Also I thought the peak rates on some white paper were in the order of 7 Mtri/sec at 200 MHz, which is about one triangle every 32 clocks. So perhaps every triangle regardless of size runs through the full 32x32 pixels per tile for triangle equation and depth test.

Isn't SGX to be on the order of up to 16 or so times the peak triangle throughput of the MBX per MHz? So do they now process any triangle per clock for triangle equ/visibility, and likely a block of pixels rather than a tile scanline?
 
Also I thought the peak rates on some white paper were in the order of 7 Mtri/sec at 200 MHz,

Yep. The problem is that they don't mention die sizes anymore for MBX.

I'd guess that MBX might work with 32*16 tiles.
 
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Not 32x8?

I figured Series5XT was where the size was bumped to 32x16.

Well it's definitely smaller than 32*32. Also are you sure you'd want fixed (macro or micro) tile sizes for something like Series5XT?

  • dynamic load balancing and on-demand task allocation at the pipeline level
  • no fixed allocation of given pixels to specific cores, enabling maximum processing power to be allocated to the areas of highest on-screen action
 
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