Nvidia Pascal Speculation Thread

[silent_guy]

Source? For what I can remember, AMD did a lot of the work, too (though I can't find the article now, I'm quite sure it was detailed somewhere that AMD did this of HBM while SK Hynix did that of HBM - AMD also has long history of developing memory standards, so I wouldn't downplay their part just because the other one is heavy weight memory manufacturer)

Source not needed: Occam's razor is sufficient unless you have a source to shows that AMD has a fab that makes DRAMs and interposers.

I'm not saying that AMD didn't heavily participate and probably was a main driver in writing down the specs. And that they obviously spent a lot of effort making sure that their own silicon worked well with that.

But I don't think HBM uses revolutionary technology in terms of analog signaling levels, or DRAM memory bank organization. IMO the real difficulty of HBM lies in the process technology of making it all happen. And that's something that ultimately was on Hynix, the interposer guys and the packaging guys to pull off.

 

[trinibwoy]

That's also the impression I got based on my limited understanding of HBM. The DRAM technology doesn't seem to be revolutionary. The hard parts were the physical interfaces and signal routing required for stacking.

 

[lanek]

Source not needed: Occam's razor is sufficient unless you have a source to shows that AMD has a fab that makes DRAMs and interposers.

I'm not saying that AMD didn't heavily participate and probably was a main driver in writing down the specs. And that they obviously spent a lot of effort making sure that their own silicon worked well with that.

But I don't think HBM uses revolutionary technology in terms of analog signaling levels, or DRAM memory bank organization. IMO the real difficulty of HBM lies in the process technology of making it all happen. And that's something that ultimately was on Hynix, the interposer guys and the packaging guys to pull off.

I dont know... just have a look at the whitepapers about HBM research who are all co-signed or set by AMD guys and university labs research. And the first are dated from more than 7 - 8years ago.

I got the feeling, but im maybe wrong, that they was allready make research about it way before they team up with SKHynix for push the project from research to the standard and production process.

I have not really the time for research them, but i think they have allready been posted here.

The design is effectively not so revolutionary, just each things had need a new solution, i think the Anand article about it is pretty good at showing how have been the developpement process from the initial research to the industrial production..Sometimes you dont need to reinvent the wheel, just use existing things for create a better one. Even the interposer fabs are a good example, they can use old 65nm old line of productions, its simple but genious, because it cost nothing on developping specific lines of production. you use what exist allready, and was nearly in the end of the road.

 

[RecessionCone]

I dont know... just have a look at the whitepapers about HBM research who are all co-signed or set by AMD guys and university labs research. And the first are dated from more than 7 - 8years ago.

I got the feeling, but im maybe wrong, that they was allready make research about it way before they team up with SKHynix for push the project from research to the standard and production process.

I have not really the time for research them, but i think they have allready been posted here.

The design is effectively not so revolutionary, just each things had need a new solution, i think the Anand article about it is pretty good at showing how have been the developpement process from the initial research to the industrial production..Sometimes you dont need to reinvent the wheel, just use existing things for create a better one. Even the interposer fabs are a good example, they can use old 65nm old line of productions, its simple but genious, because it cost nothing on developping specific lines of production. you use what exist allready, and was nearly in the end of the road.

The idea of using an older process to package chips is also not new. I enjoyed this blast from 2001 about Intel's BBUL. Very similar to today's interposers.
http://www.anandtech.com/show/834/5

 

[iMacmatician]

From WCCFTech: "Nvidia Pascal GP100 GPU Flagship Will Pack A 4096-bit Memory Bus And Four 8-Hi HBM2 Stacks."

Nvidia’s big Pascal GPU code named GP100 will feature a massive 4096bit bus and four HBM2 stacks each up to 8-Hi. The upcoming Nvidia flagship Pascal chip set to debut on TSMC’s 16nm FinFET process later next year. We have confirmed with our sources that the GPU will be made with two different variations of stacked HBM2 solutions, however both will feature a massive 4096bit memory interface just like AMD’s flagship Fiji GPU launched last month.

The first variation will pack four HBM2 stacks, each will be 4-Hi and will be clocked at 1Ghz. This will go into the traditional consumer GeForce line of GP100 based products. The second variation is also equipped with four HBM2 stacks clocked at 1Ghz, however each will be 8-Hi.

 

[3dilettante]

The numbers seem straightforward enough, although the 4-Hi variant raises a question as to whether HBM1 would serve as a value tier below HBM2. I'm not clear which counting regime they are going by with the memory speed.

 

[pjbliverpool]

So would that mean 16GB at 1TB/s for the 4-Hi version? If so it sounds like too much to me. I could see it on a Titan level product but not on a mainstream level one. Would it be possible to use 4gb chips instead for "only" 8GB or will it be as cheap by then to just use 8gb chips and go the full hog?

 

[3dilettante]

Nvidia's presentation on their plans to use HBM indicated a low-end using 4Gb density.
One possibly small change in scaling will be with the crossover to higher density than 4Gb, when the DRAM bank count doubles.
The current bank count with HBM is one area where Fury's memory is equivalent to Hawaii's. The pseudo channel mode should allow this to be more effectively utilized.

 

[Kaotik]

So would that mean 16GB at 1TB/s for the 4-Hi version? If so it sounds like too much to me. I could see it on a Titan level product but not on a mainstream level one. Would it be possible to use 4gb chips instead for "only" 8GB or will it be as cheap by then to just use 8gb chips and go the full hog?

HBM2 will be available in several densities, 4-Hi or 8-Hi as itself doesn't tell much

 

[Alatar]

Fuad seems to think the upcoming chip has 17 billion transistors:

Pascal technology will have as many as 17 billion transistors under the bonnet, Fuzilla can exclusively reveal.

http://www.fudzilla.com/news/graphics/38304-nvidia-pascal-gpu-has-17-billion-transistors

 

[lanek]

HBM2 will be available in several densities, 4-Hi or 8-Hi as itself doesn't tell much

At contrario of what wccftech say 8-16GB first.... i dont exclude to see 32gb for computing gpu''s ..


4Hi for HBM2 mean 8GB and 8Hi mean 16GB simple than that ..

 

[Kaotik]

At contrario of what wccftech say 8-16GB first.... i dont exclude to see 32gb for computing gpu''s ..
4Hi for HBM2 mean 8GB and 8Hi mean 16GB simple than that ..

By "default" HBM2 DRAM chips are 8Gbit, so 4Hi would lead to 4GB per HBM, which would be 16GB with 4096bit membus (and 32GB with 8Hi's)
In other words, they have to allow lower density DRAMs too to get to 8GB on 4096bit bus

 

[fellix]

Fuad seems to think the upcoming chip has 17 billion transistors:



http://www.fudzilla.com/news/graphics/38304-nvidia-pascal-gpu-has-17-billion-transistors

That's pretty much an educated guess. GK110 on a new process node went just over double the transistor count of GF110 (3B -> 7B), so it's only intuitive to translate the same difference between GM200 and Big Pascal.

 

[mczak]

By "default" HBM2 DRAM chips are 8Gbit, so 4Hi would lead to 4GB per HBM, which would be 16GB with 4096bit membus (and 32GB with 8Hi's)
In other words, they have to allow lower density DRAMs too to get to 8GB on 4096bit bus

Doubt that will happen. Just use 2Hi instead if you really want that (or use 2048bit bus in the first place).

 

[Kaotik]

Doubt that will happen. Just use 2Hi instead if you really want that (or use 2048bit bus in the first place).

The documentation at least doesn't go down to 2Hi

 

[mczak]

The documentation at least doesn't go down to 2Hi

Which documentation?
But anyway clearly all those presentations said "HBM2" will use 8gb dies, with the possiblity of 2-Hi, 4-Hi and 8-Hi stacks. Makes no sense to me at all that you'd want to manufacture 4-Hi with 4gb instead of 2-Hi with 8gb dies if you also do 4-Hi / 8-Hi with 8gb dies (though I'm still questioning the availability of the latter, that is I wouldn't be surprised if we'd first see 4-Hi stacks with 8gb dies).

 

[Kaotik]

Public hbm documentation, it only mentions 4hi and 8hi for what I can remember (granted I'm drunk at bar), but it did, iirc leave room for lower density dies

 

[mczak]

Public hbm documentation, it only mentions 4hi and 8hi for what I can remember (granted I'm drunk at bar), but it did, iirc leave room for lower density dies

You are right the hotchips presentation only had 4/8-hi (with 8gb dies) listed in there explicitly.
There was however also a roadmap floating around, which showed 2-hi too. Both slides can be found here:
http://www.kitguru.net/components/g...mory-chips-opens-way-for-32gb-graphics-cards/

 

[Razor1]

tsmc 16nm and pascal.

 

[pjbliverpool]

Pascal is definitely going to be my next GPU (unless AMD does something unexpectedly amazing). Can't wait!