Nvidia GT300 core: Speculation
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LOL now apparently someone at chiphell is talking about a 192SP@40nm chip. Ok by the time they all reach a unanimous verdict it might shrink even more. We're in the middle of the 212 SP count at the moment and I'm hearing bets.....
If it's anything less than GTX285, I'd be dissapointed.
It should be less even than the last report that's why I called for further bets.
aaronspink
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That's an assumption without a basis. You are assuming that both ATI and Nvidia use only the standard cells from TSMC, they use the same standard cells from TSMC, and they use the same subset of the standard cells, they have exactly the same metal stack strategy, the same clock grid strategy, use the same P&R, etc.
I would be shocked if neither Nvidia nor ATI used customs cells as part of their designs, I would be shocked if they didn't do their own analog, etc. Just because people use the same fab doesn't mean they are doing a turnkey design. While some random company may use the TSMC turnkey flow, it is highly unlikely that either Nvidia or ATI do.
This doesn't even get into things like stepper strategies: is the ATI die done as 1 die per step or 2? certainly nvidia is 1 die per step with their rumored die size. If they are both one step, then the outer edges of the nvidia exposure has more physical complications, etc. There are after all real physics issue behind things like reticule limits. Intra-reticule/die variations have been an issue for quite some time as well and scale with reticule/die size.
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Right. Given the expertise that Nvidia and ATI have, and the complexity of their own chips, I'd be highly shocked if they used TSMC's flow. These guys no doubt have their own experts on the spin process - and they most likely have their own procedures, best practices, standards, etc. no doubt from which they would instruct TSMC on what to do. TSMC just provides the capacity and capability
FWIW, Kyle of [H] wrote that he heard from two sources about this as well
http://www.hardforum.com/showpost.php?p=1034622662&postcount=36
Obviously they could all be hearing it form the same sources, who may both be right or wrong. But it seems obvious that the rumored low yields (whatever the actual %) is definitely circulating around the community
I strongly suspect that all these "sources" aren't truly independent. I suspect that many of them likely read the same piece of news on the same blog as Charlie, or know someone who did, or know someone who read a forum post by someone who read the same blog as Charlie, etc., etc., etc.
Now I've heard it all. Goodnight.
Well, no. TSMC also provides the specifications of the process and a series of design libraries. While I don't doubt that some small fraction of ATI and nVidia's designs are custom, I would be pretty surprised if the majority were (given the fast turn-around time in the graphics industry).
So, I might expect a factor of two difference in yields between the companies. But a factor of ten? That makes no sense.
Regardless, it's looking like the rumors of bad yields were just a gross misunderstanding of a translation of a blog post.
No you haven't heard even a fraction of anything. It's neither the time or place though to start any funky stories that could embarass quite a few folks.
And even if you do custom designs, you would still talk to TSMC if it can be done before implementing it.
Maybe RV870 is just a less challenging design for the available process.
aaronspink
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Fast turn around? Design cycles in the modern GPU designs are roughly on par with the design cycles of modern CPUs with significantly reduced complexity of design.
~reticule limit vs 1/2 to 2/3 reticule limit is a signficant difference for a quite frankly rather immature process and lithography flow.
they may or may not be. People assume charlie doesn't actually do any work where in fact he generally does do a significant amount of research and source checking.
I'm beginning to think GT300 is a bunch of let's say 512 RISC processors, doing SMT.
The Strongarm RISC processor was 2.5 million transistors, and had 16 KB instruction and 16 KB of data cache. So 1000 of them would fit on a 2.5 billion GPU.
Would be 16 MB of instruction and 16 MB of data cache. Share some of the caches between processors to reduced their total size and voila enough transistors to do floating/double point, texture mapping etc...
The Strongarm RISC processor was 2.5 million transistors, and had 16 KB instruction and 16 KB of data cache. So 1000 of them would fit on a 2.5 billion GPU.
Would be 16 MB of instruction and 16 MB of data cache. Share some of the caches between processors to reduced their total size and voila enough transistors to do floating/double point, texture mapping etc...
ZOMG! Its like that secret meeting that everyone had sources talking about. Sources, sources everywhere...
I thought you need more than one source to avoid plagiarism.
Thanks to AnarchX for the link: http://www.itocp.com/bbs/thread-37470-1-1.html
So now we have another superelastic chip that ranges between 452 to 533mm2. If you pull it too hard does it bounce back?
So now we have another superelastic chip that ranges between 452 to 533mm2. If you pull it too hard does it bounce back?
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