GF100 High Power Consumption: An effect from the distributed architecture?
I was thinking the other day about the chip distribution in GF100, and its possible relation with GF100 rather inneficient perf/watt. And I got the following conclusions. I would like some oppinions on it, as its something that I havent seen yet anywhere. Charlie just says that the chip is power hungry, which we all know it is, but without an explanation, other then a bad 40nm process, thats just a la palice truth.
So, to kick it off, what if the chip is power hungry mainly because of its distribution? My argument follows:
In a not distributed architecture, without GPCs, and TMU's attached to the SMs, there would be just a single TMU structure right? So all the "energy costs" associated with the TMU's are concentrated in "one space". Sort of like economy fixed+variable costs, if you know what I mean. For a given TMU there would be fixed costs, but as all TMU's are in the same place, they get really diluted and negligible.
Now picture GF100, with the TMU's distributed in the GPC's, through the SM's. Here you would have a lot of fixed "energy costs" multiplicated by the number of TMU's blocks. In this case the fixed costs are not diluted by the low number of TMU's in each block, exacerbating total energy cost.
To put it in a more simple way: where before you had 1xFixed Cost, now you have 16xFixed Cost. Of course each of the 16 fixed energy cost is lower than the 1xFixed Cost of before, but probably not 1/16 of it. In the end power consumption would be higher.
What do you think? Does it make sense? I think this could be the ground for the GF100 architecture is broken stance.