First, let me show some good will by starting with what I agree I was either wrong or severely imcomplete about (and of course I may be wrong about more):
Of course, I have to admit that I suspect NVIDIA has started to name spins for marketing reasons. Specifically, Tegra APX 2600 is an 'A3' even though it includes significant silicon layer changes compared to the APX 2500. I assume they did that so their customers would be less scared of switching most existing design-ins to that revision. So it's possible that they'd name A3 what should logically be a B1, and then you'd be even more right.
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Now the disagreements/misunderstandings:
) expecting the reverse. Of course *if* they are themselves very uncertain whether A2 is good to go, they wouldn't want to waste all $50M and I'd be crazy to deny that.
That's perfectly reasonable, and indeed if you believe you could have that level of information then it's not fair of me to reject that reasoning. I was simply assuming that since you weren't certain whether Fermi did tape-out in W42, you probably couldn't truly know the amount of activity (versus a simple 'it has or hasn't taped-out') around the derivatives. But of course, what you know is not what your sources (or their own sources) know, and in foresight it seems perfectly reasonable that you'd know about one but not the other.Groo The Wanderer said:
You're right; I certainly don't know, although I obviously agree they couldn't be minor ones if it took 7 weeks. It does seem rather extreme to claim that a completely new architecture should only take 2 weeks to respin, including bringup; but 7 weeks is still clearly more than you'd expect. I'll also admit I assumed that you didn't know either; but I can certainly believe that if you say so.Groo The Wanderer said:
That's perfectly reasonable; although as silent_guy indicated, they'd probably park the risk wafers before the first metal layer since the time difference is so small. And if the silicon layer is affected, then I'd expect the 'respin' to be named B1, not A3.MfA said:
Of course, I have to admit that I suspect NVIDIA has started to name spins for marketing reasons. Specifically, Tegra APX 2600 is an 'A3' even though it includes significant silicon layer changes compared to the APX 2500. I assume they did that so their customers would be less scared of switching most existing design-ins to that revision. So it's possible that they'd name A3 what should logically be a B1, and then you'd be even more right.
I'm getting a bit tired (nearly midnight here), but I think I made it 4 weeks from production lots and *6 weeks* from hot lots: 21-17=4; 21-15=6. But I agree: even then, for an ultra-pessimistic scenario that is clearly too optimistic. Add at least 2-3 weeks to that, assuming no major SW/driver issues (which seem rather unlikely since they'll have had the A1s for 9 months then!) and possibly even more due to issues that only crop up in the real-world rather than theoretical analysis.Grall said:
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Now the disagreements/misunderstandings:
I used Charlie's own numbers for this: 7 weeks for a full tape-out, 4 weeks for a respin based on wafers parked before the metal layers. Those seem perfectly reasonable to me.dkanter said:
Oh, I agree with the numbers. What I took exception with is that you said 'assuming Nvidia parked a few wafers' in that paragraph whereas later you refer to risk wafers as if they were a certainty and the only question is whether they will need to be scrapped. I do realize that you know they are used for both things, I simply found the article's phrasing a bit misleading.Groo The Wanderer said:
Well, nothing forces them to produce all of them before getting the hot lots back, and remember there is also both a direct and an indirect (brand reputation/investor confidence/...) loss from being even more late to market. So producing $10-15M, for example, may be a good compromise. However remember this: there's no reason for them to order so many of them in advance if they didn't plan to use them fast. I know yields went back *down* at TSMC, but surely they were (naivelyGroo The Wanderer said:
) expecting the reverse. Of course *if* they are themselves very uncertain whether A2 is good to go, they wouldn't want to waste all $50M and I'd be crazy to deny that.Mostly (but not exclusively) bring up & early chips for the driver guys, obviously. Which is also why I'm confused that a respin should only take 2 weeks once you've got silicon back (we do agree 7 is not a good sign at all).Groo The Wanderer said:
I'm not aware of any demo that made extensive use of OGL/DX, but what do you mean by 'simulated graphics'? Do you mean CUDA-generated stuff, or are you claiming they were unable to demo anything (even CUDA) on real silicon? I do have good reason to believe they weren't lying when they claimed N-Body ran on real silicon in real time (live), but then again I'm not sure we disagree on that.Groo The Wanderer said:
