Making sense of threads/vectors
To me, the most consistent and accurate terminology seems to be that
warp/wavefronts size := vector lanes
and
in CUDA speak, (threads/block)/(warp size) := number of threads
- G80
has at most 24 hw threads per core, (16 cores overall), where each thread executes 32 wide simd instructions
- GT200
has at most 32 hw threads per core, (30 cores overall), where each thread executes 32 wide simd instructions
- Larrabee
has at most 4 hw threads per core, (?? cores overall), where each thread executes 16 wide simd instructions. LRB also implements multiple sw threads per hw thread for additional latency hiding
- Cypress
cypress has at most ?? hw threads per core, (20 cores overall), where each thread executes 64 wide simd instructions. needs lot of ILP in code to reach peak performance.
- Cell
and cell has at most 1 hw threads per core, (8 cores overall), where each thread executes 4 wide simd instructions (counting only spe's)
- Nehalem
has at most 2 hw threads per core, (4 cores overall), where each thread executes 4 wide simd instructions. needs lot of ILP in code to reach peak performance.
- Fermi
has at most 48 hw threads per core, (16 cores overall), where each thread executes 32 wide simd instructions
ALL chips above allow simd divergence to be handled, but with some performance penalty. Programming models are of course different depending upon vendor.
Chips traditionally called CPU's expose SIMD ISA to programmer, leaving it them to write SIMD code, (or to autovectorizing compilers).
Chips traditionally called GPU's expose do not expose SIMD ISA to programmer. They usually write scalar code which is vectorized in hardware.
Some chips, (like cypress, nehalem etc.) expect needs lot of ILP in code to reach peak performance.
Vectors vs threads don't have to be mutually exclusive.
What do the specialists of B3D think?
