nvidia "D8E" High End solution, what can we expect in 2008?

Twinkie said:
If the full G92 does indeed have a 384bit bus, then how does the frame buffer size work out?
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If this is the case, perhaps cleverly. If the memory crossbar is fully decoupled you can include as many PTP channels as required...
If 8800GT G92 -> 7C/256bit & 8800GTS G92 -> 8C/256bit then New SKU G92 -> 10C or 12C/256bit or 384bit or 512bit.
 
ShaidarHaran said:
AMD had a 512-bit (external) MC interface with 1024-bit internal precision and a ring bus w/accompanying ring stops to accomodate. This is far more complex than NV's 6x64-bit + crossbar approach.
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In terms of area, both ring bus and crossbar must be small compared to the rest of the logic, because there's really not a lot of intelligence in it. A ring is less efficient wrt area to reach the same performance, but that's just a matter of increasing bus width and FIFO's along the way. More area, but not excessively so.

The real complexity, both algorithmically and wrt area, is in the individual per chip memory controllers. In the presence of multiple incoherent request streams, to squeeze the maximum amount of bandwidth out of a memory chip, you need deep FIFO's, preferably for each individual requester, to group coherent requests, and you need the logic to detect those groups. I wouldn't be surprised about a 10:1 area difference between those arbiters vs the transport fabric.

Other than AMD claiming that they have a very advanced programmable arbiter, we don't know anything about either implementation. This makes speculation about their size and complexity an exercise in futility.
It's not even all that far-fetched to speculate that the MC of a G80 is larger than that of R600. Unlikely, yes, but not impossible.
 
DegustatoR said:
Then it's 100% sure not the same G92 chip that's used in GF8800GTs.
Cause this chip has 256 bit only, period.
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And you know this from where?

We have a 754M/300mm² die and NV has the easy-possibility to scale MC in 64Bit-steps, it would be strange if G92 is only 256Bit...
 
AnarchX said:
Interesting, any more information/pictures about this?
And in G80-GTS BIOS are entries to disabled MC?
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I'm not the one you should talk to about this :)
But AFAIU there are only 4 ROPs and 64-bit MCs in BIOS, no disabled ROPs or anything which should be there one way or another if G92 has 6 ROPs/MCs.
So i'm pretty sure that G92 is 256-bit only, nothing more.
 
Hmmm... so lets see what will happen in January/February...

But it would be still a bit strange/stupid if NV does not use this feature of their architecture, on a 300mm²-64TMU-GPU... :???:
 
AnarchX said:
Hmmm... so lets see what will happen in January/February...

But it would be still a bit strange/stupid if NV does not use this feature of their architecture, on a 300mm²-64TMU-GPU... :???:
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Please don't forget that the G92 chip including the NV-IO chip & VP2 hardware engine into the G92 core too. That would take up a bit space on the core then (I hope) ;)
 
satein said:
Please don't forget that the G92 chip including the NV-IO chip & VP2 hardware engine into the G92 core too. That would take up a bit space on the core then (I hope) ;)
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This stuff should be ~xxM transistors and even <10mm² on die.

Another question is also, when G92 is only 256Bit/16ROPs, why NV made it with 64TMUs/128SPs, when for example 6C+high clock would be cheaper in production?
 
AnarchX said:
This stuff should be ~xxM transistors and even <10mm² on die.

Another question is also, when G92 is only 256Bit/16ROPs, why NV made it with 64TMUs/128SPs, when for example 6C+high clock would be cheaper in production?
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Probably, the DP (double precision) may ring the bell in what NV have done to the G92 core. The DP was rumoured to be enabled on the card like GPGPU and workstation class, it's my guess anyway.
 
AnarchX said:
Another question is also, when G92 is only 256Bit/16ROPs, why NV made it with 64TMUs/128SPs, when for example 6C+high clock would be cheaper in production?
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Rising memory speeds and GDDR4 can be your answer.
They'll be able to reach GTX bandwidth with faster memory and 256-bit bus.
Ultra will remain unchalleged though.
 
AnarchX said:
Another question is also, when G92 is only 256Bit/16ROPs, why NV made it with 64TMUs/128SPs, when for example 6C+high clock would be cheaper in production?
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Doesn't it perform well enough for you? :) The TU ratio is an evolution of the G84 & they were able to address the mid-range performance issues of the 8600 series by keeping the full complement of ALUs. The "sacrifice" was 16 ROPs/256bit to hit the mid-range price points. Higher clock is a riskier solution to Nvidia, that can be offset with multiple-clock domains. Also, don't forget redundancy. There's a good chance of a 6C G92 SKU.
 
trinibwoy said:
That's kinda sad. IIRC the GX2 wasn't much of a seller and had a butload of scaling issues.
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But don`t you know it could be strange if D9E were Dual G92??

Let`s see.. A few days ago Dailytech revealed codenames for NVIDIAs upcoming GPUs.

D8M
D8P

D9M
D9P
D9E

G92=D8P so D9E must be 2xD8P.... So what about D9P?? If G9x is still GF8 generation it seems that D9x is another GPU??
I think if D9E is supposed to be Dual GPU card it is more likely it will be Dual D9P not D8P.

I really hope D9E is NOT GX2 like card.
 
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