I had stated earlier that the programmable tessellation unit was going to be in NV35. It's not clear to me anymore that this is the case. Apparently this will be in a 4Q'03 part, which leads me to believe that it will be NV40, not NV35. This part will also contain a completely revamped unified shading model. This means that both vertex and pixel shaders will share the exact same ISA and constructs. In other words, pixel shaders will also have access to constant based/dynamic branching. What's most interesting is that nVidia is not the only company doing these things in that timeframe.
There was some talk in one of the threads about how peak gigaflops were calculated. I think someone already mentioned this, but they base it on MAD which is counted as two flops throughput per cycle per unit. Latency is higher, but it's essentially masked by the pipeline unless there is a dependency.
I don't have any further info on NV30 other than that it's back and "operational". I don't know if operational implies demo-able at comdex or not.
There was some talk in one of the threads about how peak gigaflops were calculated. I think someone already mentioned this, but they base it on MAD which is counted as two flops throughput per cycle per unit. Latency is higher, but it's essentially masked by the pipeline unless there is a dependency.
I don't have any further info on NV30 other than that it's back and "operational". I don't know if operational implies demo-able at comdex or not.