NV30 in-depth block diagram in digit-life article

[jpeter]

I don´t know much but it
looks interesting.

For a strange reason the article doesn't finish.

http://www.digit-life.com/articles2/gffx/index.html

 

[RussSchultz]

Interesting, it mentions a 'tile buffer', plus 3 integrated TDMS.

 

[DeathKnight]

Tile optimization: caching, compression and Early Cull HSR

Some tiling in there after all?

 

[cho]

UncleSam(the author) told me that is only mean "early Z cull oа tile blocks from triangles" .

 

[Nappe1]

Interesting, it mentions a 'tile buffer', plus 3 integrated TDMS.

what makes me wonder is that acording to that block diagram, GeForce FX would have 2 RAMDACs, TV-encoder/decoder and 3 TDMS units integrated. and that if something, sounds a lot to be on chip. And how they still have only 2 DVIs if they have 3 TDMSes? what's the last one for?

 

[RussSchultz]

I wonder if you could use the TDMS for inter-chip signalling (i.e. multichip configurations)

 

[stevem]

[quote:"jpeter"]For a strange reason the article doesn't finish.[/quote]

It's been like that since yesterday.

[quote:"Nappe1"]...TV-encoder/decoder and 3 TDMS units integrated. and that if something, sounds a lot to be on chip.[/quote]

It's interesting as they specify both integrated TVO as well as an interface for an external TVO chip. TDMS & VIVO appear to be handled via external chips on the existing board design (P128). Perhaps YPbPr for HDTV is also supported.

 

[arjan de lumens]

Most likely, it is the same kind of tiling that we know from P10, XP4, Glaze3d, all Radeon series chips and probably Geforce1-4 as well: it subdivides a polygon into tiles, and for each tile draws the portion of the polygon that falls within the tile, then moves on to next tile until it is finished with the polygon - and only then does it start drawing the next polygon. A tiled framebuffer cache.

TMDS, as used by DVI, has a bandwidth of a little less than 1 GByte/sec per channel (6 differential pairs; 1.65 Gbit/sec/pair; 10 bits per byte encoding), so interchip communication would probably be limited to one chip acting as a master or passthrough for the other chip in an AFR or SLI setup.

 

[maskrider]

It's interesting as they specify both integrated TVO as well as an interface for an external TVO chip. TDMS & VIVO appear to be handled via external chips on the existing board design (P128). Perhaps YPbPr for HDTV is also supported.

Pictures of the current boards that we've seen have Silicon Image DVI transceivers on the board.

Is that block diagram up to date ?

[edit]
Oops, the bullet list has this one that I have missed

Three TDMS interfaces for external DVI interface chips

And it should be TMDS, not TDMS.
[/edit]

 

[KimB]

I'm curious...with those three TMDS transmitters, can they actually drive three independent displays?

With only two RAMDACs, it seems concievable that one of the three possible DVI displays may only be able to run in clone mode, which seems even more probable when you look at the block diagram (two arrows pointing to DVI).

Since we haven't seen anything hyped about something akin to Matrox' "Surround Gaming," I wonder why this chip has three TMDS transmitters at all?

Assuming, of course, that this article is not in error. Given the unfinished nature (How could they put out a half-page like that? Pffft), this info, if not reinforced elsewhere, doesn't seem to be 100% trustworthy.

 

[no_way]

its probably Z-pyramid hierarchical Z buffer, using "tiling", like described in NVs patent that nAo posted recently.
here

This modified version of hierarchical tiling with coverage masks is believed to be the fastest algorithm available for hierarchical z-buffering of polygons

 

[Dave Baumann]

That block diagram also shows 3 vertex shaders, which obviously isn't correct.

 

[Dave Baumann]

its probably Z-pyramid hierarchical Z buffer, using "tiling", like described in NVs patent that nAo posted recently.
here

This modified version of hierarchical tiling with coverage masks is believed to be the fastest algorithm available for hierarchical z-buffering of polygons

If you look at the arrangement of the block diagram all the 'yellow stuff' is framebuffer operations - so going by that diagram the HSR logic is still consistent with per pixel operations rather then geomtry. There's nothing to suggest they have anything radically different than GeForce4 - other than it can reject more pixels per clock.

 

[stevem]

And it should be TMDS, not TDMS.

Yes. I noticed I'd typed it wrong before, but continued with it. Brain fade...

That block diagram also shows 3 vertex shaders, which obviously isn't correct.

Edit:
Reiterated here: http://www.digit-life.com/articles2/gffx/index2.html
Does GFFX fp array have Mosaic overtones...?

 

[no_way]

the article seems to be complete now.

 

[maskrider]

And it should be TMDS, not TDMS.

Yes. I noticed I'd typed it wrong before, but continued with it. Brain fade...

I mean it is wrong in the article and the block diagram, not to your post.

 

[stevem]

Probably why I continued with it, then...

Perhaps they've reproduced the diags introducing errors (?) & they're not copied directly from the press kit.

 

[psurge]

DaveB,

Why would you want HSR logic next to the vertex shaders?
You are culling in screenspace, so it should be placed close to the rasterizer.

AFAICS you would want a heirarchical rasterization scheme for triangles, to go with the HZ pyramid. To reject geometry, you would send some kind of bounding hull (box for example), rasterize it, and if it is not completely discarded by the Z-pyramid, send the geometry.

Serge