Main CELL core is a MIPS design

[Fafalada]

Includes some (all?) of the PS2’s Emotion Engine ISA.

"All" of EE ISA would include entire MIPS and VU. Given that SPE SIMD is a 180 change in direction away from VUs, we can safely assume there's nothing of VU ISA in there.
R5900 on the other hand did have a pretty nifty integer SIMD, which was very alike to VMX (although it had some very specific horizontal ops, but anyway), so perhaps some of that crossed over to SPE.

 

[j^aws]

Perhaps this IBM patent has something to do with this...?

Computer system supporting control transfers between two architectures

EDIT:

Fixed fuxx0red link!

 

[Fox5]

Speaking of interesting tidbits, I just heard not too long ago that XeCores are x86-PPC hybrid too.

An in order x86 cpu trying to run out of order xbox code?

even though it's been stated before that Cell is not bi-endian

I thought the Power architecture was one of the few that was bi-endian...

 

[rendezvous]

An in order x86 cpu trying to run out of order xbox code?

It's not the code that is out of order.
It is the CPU that is executing the instructions out of order.

 

[Carl B]

Well and the cores are PPC (well that's our knowledge of it); it's the x86 that would be the big surprise here.

 

[j^aws]

Well and the cores are PPC (well that's our knowledge of it); it's the x86 that would be the big surprise here.

The canned PPC 615 from ~10 years ago already did this. See my above link...

 

[Carl B]

The canned PPC 615 from ~10 years ago already did this. See my above link...

Well I was just talking about Fafalada's rumor with regard to the XeCPU cores, but if either one of them ended up being x86 compatible - I mean, that would just be insane!

It's definitely the subject of that patent, but wouldn't something have leaked out by now?

 

[Fafalada]

Ok before this goes too far - I was just being sarcastic trying to post something equally silly as the starting quote of the thread

 

[Carl B]

Ok before this goes too far - I was just being sarcastic trying to post something equally silly as the starting quote of the thread

LOL, don't worry Faf - for my part I knew you were just talking in the context of 'something crazy you'd heard.'

Putting the main topic aside though, I do wonder if and when we'll see variant 'Cell' architectures arise based on alternative 'main' core architectures; and if we do, whether the SPE's will remain the same.

 

[j^aws]

The canned PPC 615 from ~10 years ago already did this. See my above link...

Well I was just talking about Fafalada's rumor with regard to the XeCPU cores, but if either one of them ended up being x86 compatible - I mean, that would just be insane!

It's definitely the subject of that patent, but wouldn't something have leaked out by now?

Well, I was thinking more for backwards compatibility. E.g. x86->PPC for X360 and MIPS->PPC for PS3. This stuff isn't exactly new and Transmeta used something similar recently.

@Faf, boys who cry 'wolf' will eventually meet their DEATH!

 

[darkblu]

@Faf, boys who cry 'wolf' will eventually meet their DEATH!

as opposed to all the rest who will never meet theirs... wait :?

 

[Fox5]

An in order x86 cpu trying to run out of order xbox code?

It's not the code that is out of order.
It is the CPU that is executing the instructions out of order.

But the code was written expecting the cpu to have the ability to execute out of order, the x360 cpu will need different optimizations.
Plus, isn't x86 code supposed to be virtually unworkable without out of order execution?

 

[j^aws]

Off topic:

@Faf, boys who cry 'wolf' will eventually meet their DEATH!

as opposed to all the rest who will never meet theirs... wait :?

Eaten by wolves for a premature and horrible death! I thought it was a well known tale but...nevermind!


On topic:

Talking about Transmenta, IIRC, there was some recent news with their involvement with SPUs and PS3...but I don't think it involved emulation of any sort...

 

[Carl B]

The Transmeta agreement was in order to emulate an SPE environment on x86 for programming/debugging purposes I believe.

Transmeta will be offering an SPE optimizer and software that will let developers effectively program for the Cell processor and its seven SPEs. The tools will allow statistical process control (SPC) simulation on PCs and will also let programmers debug and tune their programs with runtime info. Transmeta's tools will be shipped to developers in Q4 2005.

Link

 

[Barbarian]

The SPU ISA is a brand new one, that Sony/Toshiba created and IBM helped and implemented. Having said that, SPU ISA has PowerPC written all over it, from the IBMish instruction names to big endian and what not.
There is no way the SPU can run any MIPS or VU code directly.
Unless Sony has some uber emulator, I bet they'll include the EE+GS in PS3 for backwards compatibility.

 

[j^aws]

The Transmeta agreement was in order to emulate an SPE environment on x86 for programming/debugging purposes I believe.

Transmeta will be offering an SPE optimizer and software that will let developers effectively program for the Cell processor and its seven SPEs. The tools will allow statistical process control (SPC) simulation on PCs and will also let programmers debug and tune their programs with runtime info. Transmeta's tools will be shipped to developers in Q4 2005.

Link

Ah thanks for link. Q4? Same time as PS3 reference kits...

Seems like a cheap way for QC/PA on X86 H/W without tying up expensive, reference PS3 kits...

 

[Fafalada]

Unless Sony has some uber emulator, I bet they'll include the EE+GS in PS3 for backwards compatibility.

Then they'll need IOP and it's memory as well - and that's a heck of a lot of chips when they serve no purpose beyond emulation.
I think EE(along with IOP and SPU and co.) wouldn't be too hard to emulate really - GS is more iffy on the other hand...

 

[Barbarian]

I don't think the IOP was ever a separate chip, was it? They might need to rework it's memory controller to access xdram, and this shouldn't be too hard since the IOP only needs to run at 40Mhz. Plus you get PS1 compatibility as a bonus.
Sony already has EE+GS on 1 chip AFAIK. GS's EDRAM must be on the same chip too. It will have the same trouble with the memory controller, but that's way easier than writing 100% bullet proof emulator.

 

[rendezvous]

But the code was written expecting the cpu to have the ability to execute out of order, the x360 cpu will need different optimizations.
Plus, isn't x86 code supposed to be virtually unworkable without out of order execution?

We are getting way off topic here.
As long as you don't have any unsupported instructions the code that the compiler has optimized for a P4 will run on a 386, only not as fast as if it would have been optimized for a 306. There are many aspects the compliler has to consider when optiomizing and OoO execution is just one.

 

[Fafalada]

I don't think the IOP was ever a separate chip, was it?

It was/is, and so were the SPU2 and asociated 2x2MB of DRAM. I don't think Sony ever got the rights to integrate it all to single chip.

Sony already has EE+GS on 1 chip AFAIK. GS's EDRAM must be on the same chip too. It will have the same trouble with the memory controller, but that's way easier than writing 100% bullet proof emulator.

Easier perhaps, but more costly in the long run. Possibly much more so.